Semiconductor-on-insulator with back side heat dissipation
View Patent ↗Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.
1. A method of fabricating an integrated circuit, the method comprising:
preparing a semiconductor-on-insulator wafer for processing, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate;
forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region;
bonding a handle wafer to a top side of said semiconductor-on-insulator wafer;
after bonding said handle wafer to said semiconductor-on-insulator wafer, removing said substrate from a backside of said semiconductor-on-insulator wafer;
forming an excavated insulator region in said insulator layer from a back side of said semiconductor-on-insulator layer, said excavated insulator region exposing a portion of said active device; and
depositing an electrically insulating thermal dissipation layer on said excavated insulator region;
wherein said excavated insulator region defines a remaining section of insulator material that is laterally coextensive with said channel region of said active device.
2. The method of claim 1 , further comprising:
passivating a group of interface states by using a low temperature thermal anneal, said group of interface states being formed during said forming of said excavated insulator region;
wherein said electrically insulating thermal dissipation layer comprises a same material as said insulator layer.
3. The method of claim 1 , wherein
said excavated insulator region is laterally coextensive with both said source region and said drain region of said active device.
4. The method of claim 1 , further comprising:
removing a portion of said electrically insulating thermal dissipation layer to form an excavated thermal dissipation layer region; and
depositing a metal contact in said excavated thermal dissipation layer region;
wherein said metal contact serves as an electrical contact for said active layer.
5. The method of claim 1 , further comprising:
bonding a permanent handle wafer to said thermal dissipation layer; and
removing said handle wafer from said semiconductor-on-insulator wafer.
6. The method of claim 5 , wherein
said permanent handle wafer consists essentially of an electrically insulating thermally conductive material.
7. The method of claim 5 , wherein
said permanent handle wafer comprises high-resistivity silicon.
8. A method of fabricating an integrated circuit, the method comprising:
providing a semiconductor-on-insulator wafer, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate;
forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region;
bonding a handle wafer to said semiconductor-on-insulator wafer;
after bonding said handle wafer to said semiconductor-on-insulator wafer, removing a portion of said substrate from said semiconductor-on-insulator wafer using a chemical etch;
after removing said substrate from said semiconductor-on-insulator wafer, removing a portion of said insulator layer from a back side of said semiconductor-on-insulator wafer to form an excavated insulator region and to leave an unexcavated insulator region; and
depositing a thermal dissipation layer on said excavated insulator region;
wherein said unexcavated insulator region is laterally coextensive with said channel region of said active device, and exposes a portion of said active device.
9. The method of claim 8 , wherein
said excavated insulator region is laterally coextensive with both said source region and said drain region of said active device.
10. The method of claim 9 , further comprising:
patterning said thermal dissipation layer to expose a bottom side of said insulator layer in said unexcavated insulator region;
wherein said thermal dissipation layer is electrically conductive and provides a first electrical contact to said drain region and a second electrical contact to said source region.
11. The method of claim 8 , wherein
said thermal dissipation layer is electrically insulating.
12. The method of claim 11 , further comprising:
removing a portion of said electrically insulating thermal dissipation layer to form an excavated thermal dissipation layer region; and
depositing a metal contact in said excavated thermal dissipation layer region;
wherein said metal contact serves as an electrical contact for said active layer.
13. The method of claim 12 , wherein:
heat channels more efficiently laterally through said active region and vertically through said source region to said thermal dissipation layer than vertically through said active region and vertically through said insulator layer to said thermal dissipation layer.
14. The method of claim 11 , further comprising:
removing a portion of said electrically insulating thermal dissipation layer to form an excavated thermal dissipation layer region; and
depositing a metal contact in said excavated thermal dissipation layer region;
wherein said metal contact is not electrically connected to said active layer.
15. The method of claim 8 , further comprising:
bonding a permanent handle wafer to said thermal dissipation layer; and
removing said handle wafer from said semiconductor-on-insulator wafer;
wherein said permanent handle wafer consists essentially of an electrically insulating thermally conductive material.
16. The method of claim 15 , wherein
said thermal dissipation layer is planarized prior to bonding said permanent handle wafer to said thermal dissipation layer; and
said thermal dissipation layer covers an entire back side of said semiconductor-on insulator layer prior to bonding said permanent handle wafer.
17. The method of claim 16 , wherein
said permanent handle wafer comprises high-resistivity silicon.
18. A method of fabricating an integrated circuit, the method comprising:
providing a semiconductor-on-insulator wafer, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate;
forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region;
bonding a handle wafer to said semiconductor-on-insulator wafer;
after bonding said handle wafer to said semiconductor-on-insulator wafer, removing said substrate from said semiconductor-on-insulator wafer;
after removing said substrate from said semiconductor-on-insulator wafer, uniformly removing said insulator layer from a back side of said semiconductor-on-insulator wafer;
passivating a group of interface states by using a low temperature thermal anneal, said group of interface states being located on said back side of said semiconductor-on-insulator wafer; and
after removing said insulator layer from said back side of said semiconductor-on-insulator wafer, depositing a thermal dissipation layer on said back side of said semiconductor-on-insulator wafer;
wherein said thermal dissipation layer comprises a same material as said insulator layer.
19. The method of claim 18 , further comprising
depositing a layer of material with high thermally conductivity on said thermal dissipation layer.
20. The method of claim 19 wherein
said thermal dissipation layer has an average thickness of 5 to 20 nanometers, and a thickness uniformity of within plus or minus 5 percent of said average thickness.
21. The method of claim 20 , further comprising:
removing a portion of said electrically insulating thermal dissipation layer to form an excavated thermal dissipation layer region; and
depositing a metal contact in said excavated thermal dissipation layer region.
22. The method of claim 21 , wherein:
heat channels more efficiently laterally through said active region and vertically through said source region to said thermal dissipation layer than vertically through said active region and vertically through said insulator layer to said thermal dissipation layer.