External signal input circuit of semiconductor memory
View Patent ↗In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.
1. An external signal input circuit of a semiconductor memory, comprising:
an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and
a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory in response to a rank signal and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration in response to the rank signal.
2. The external signal input circuit according to claim 1 , wherein the rank signal defines the rank configuration as a single-rank configuration or a multi-rank configuration.
3. An external signal input circuit of a semiconductor memory, comprising:
a first input unit configured to receive a first external signal to generate a first internal signal;
a second input unit configured to receive a second external signal to generate a second internal signal;
a first control unit configured to receive the first internal signal and output the first internal signal; and
a second control unit configured to block an output of the second internal signal in response to a rank signal.
4. The external signal input circuit according to claim 3 , wherein the rank signal defines the rank configuration as a single-rank configuration or a multi-rank configuration.
5. An external signal input circuit of a semiconductor memory, comprising:
a first input unit configured to output a first buffering signal as a first internal signal, the first buffering signal being generated by receiving a first external signal; and
a second input unit configured to select one of the first buffering signal and a second buffering signal, generated by receiving a second external signal, in response to a rank signal and to output the selected buffering signal as a second internal signal,
wherein the second input unit is configured to block an input of the second external signal in response to the rank signal.
6. The external signal input circuit according to claim 5 , wherein the second input unit comprises:
a buffer configured to receive the second external signal in response to a control signal and to generate the second buffering signal;
a control section configured to receive an enable signal and to output the enable signal as the control signal based on the rank signal; and
a setup/hold section configured to select one of the first buffering signal and the second buffering signal based on the rank signal and to control a setup/hold time of the selected buffering signal.