Memory test circuit, semiconductor integrated circuit and memory test method
View Patent ↗A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data for the redundancy portion in test data representing data for the actual array portion and the redundancy portion as input selecting data in a redundancy BIST mode (RBM); an input data switching circuit outputting the test data as output test data to the memory in a direct BIST mode (DBM), and outputting data obtained by adding redundancy bits to the input selecting data as the output test data to the memory based on the input selecting data and output redundancy codes representing redundancy codes in the RBM; an output data switching circuit outputting data obtained by removing the redundancy bits from read data as output selecting data based on the read data from the memory and the output redundancy codes in the RBM; and a memory BIST comparator checking a value of the read data with a checking expectation value to output a checking result as a test result in the DBM, and checking a value of the output selecting data with an expectation value for the actual array portion in the checking expectation value to output a checking result as the test result in the RBM.
1. A memory test circuit which tests a test target memory including an actual array portion and a redundancy portion, comprising:
an input data selector configured to output first test data excluding data for said redundancy portion in test data representing data for said actual array portion and said redundancy portion as input selecting data in a redundancy memory BIST (Built In Self Test) mode;
an input data switching circuit configured to output said test data as output test data to said test target memory in a direct memory BIST mode, and output data obtained by adding redundancy bits to said input selecting data as said output test data to said test target memory based on said input selecting data and output redundancy codes representing redundancy codes in said redundancy memory BIST mode;
an output data switching circuit configured to output data obtained by removing said redundancy bits from read data as output selecting data based on said read data from said test target memory and said output redundancy codes in said redundancy memory BIST mode; and
a memory BIST comparator configured to check a value of said read data with a checking expectation value to output a result of said checking as a test result in said direct memory BIST mode, and check a value of said output selecting data with an expectation value for said actual array portion in said checking expectation value to output a result of said checking as said test result in said redundancy memory BIST mode.
2. The memory test circuit according to claim 1 , wherein said input data switching circuit includes:
a redundancy input data switching circuit configured to output redundancy input data obtained by adding said redundancy bits to said input selecting data based on said input selecting data and said output redundancy codes in said redundancy memory BIST mode, and
a redundancy direct data selector configured to output said test data as said output test data to said test target memory in said direct memory BIST mode, and output said redundancy input data as said output test data to said test target memory in said redundancy memory BIST mode.
3. The memory test circuit according to claim 1 , wherein said output data switching circuit includes:
a redundancy output data switching circuit configured to output redundancy output data obtained by removing said redundancy bits from said read data based on said read data and said output redundancy codes in said redundancy memory BIST mode, and
an output data selector configured to output a first read data obtained by removing read data for said redundancy portion from said read data as said output selecting data to said memory BIST comparator in said direct memory BIST mode, and output said redundancy output data as said output selecting data to said memory BIST comparator in said redundancy memory BIST mode,
wherein said memory BIST comparator checks said read data for said redundancy portion and said output selecting data with said checking expectation value to output a result of said checking as said test result in said direct memory BIST mode, and checks a value of said output selecting data with an expectation value for said actual array portion in said checking expectation value to output a result of said checking as said test result in said redundancy memory BIST mode.
4. The memory test circuit according to claim 1 , further comprising:
a memory BIST controller configured to output said test data and said checking expectation value for said test data.
5. The memory test circuit according to claim 1 , further comprising:
a test access port controller configured to output test redundancy codes representing said redundancy codes; and
an input data selector configured to output said test redundancy codes as said output redundancy codes to said input data switching circuit in said redundancy memory BIST mode.
6. The memory test circuit according to claim 1 , wherein said redundancy codes is obtained from said test result in a case where said direct memory BIST mode is performed.
7. A semiconductor integrated circuit comprising:
a test target memory configured to include an actual array portion and a redundancy portion; and
a memory test circuit configured to test said test target memory,
wherein said memory test circuit includes:
an input data selector configured to output first test data excluding data for said redundancy portion in test data representing data for said actual array portion and said redundancy portion as input selecting data in a redundancy memory BIST (Built In Self Test) mode,
an input data switching circuit configured to output said test data as output test data to said test target memory in a direct memory BIST mode, and output data obtained by adding redundancy bits to said input selecting data as said output test data to said test target memory based on said input selecting data and output redundancy codes representing redundancy codes in said redundancy memory BIST mode,
an output data switching circuit configured to output data obtained by removing said redundancy bits from read data as output selecting data based on said read data from said test target memory and said output redundancy codes in said redundancy memory BIST mode, and
a memory BIST comparator configured to check a value of said read data with a checking expectation value to output a result of said checking as a test result in said direct memory BIST mode, and check a value of said output selecting data with an expectation value for said actual array portion in said checking expectation value to output a result of said checking as said test result in said redundancy memory BIST mode.
8. The semiconductor integrated circuit according to claim 7 , wherein said input data switching circuit includes:
a redundancy input data switching circuit configured to output redundancy input data obtained by adding said redundancy bits to said input selecting data based on said input selecting data and said output redundancy codes in said redundancy memory BIST mode, and
a redundancy direct data selector configured to output said test data as said output test data to said test target memory in said direct memory BIST mode, and output said redundancy input data as said output test data to said test target memory in said redundancy memory BIST mode.
9. The semiconductor integrated circuit according to claim 7 , wherein said output data switching circuit includes:
a redundancy output data switching circuit configured to output redundancy output data obtained by removing said redundancy bits from said read data based on said read data and said output redundancy codes in said redundancy memory BIST mode, and
an output data selector configured to output a first read data obtained by removing read data for said redundancy portion from said read data as said output selecting data to said memory BIST comparator in said direct memory BIST mode, and output said redundancy output data as said output selecting data to said memory BIST comparator in said redundancy memory BIST mode,
wherein said memory BIST comparator checks said read data for said redundancy portion and said output selecting data with said checking expectation value to output a result of said checking as said test result in said direct memory BIST mode, and checks a value of said output selecting data with an expectation value for said actual array portion in said checking expectation value to output a result of said checking as said test result in said redundancy memory BIST mode.
10. The semiconductor integrated circuit according to claim 7 , wherein said memory test circuit further includes:
a memory BIST controller configured to output said test data and said checking expectation value for said test data.
11. The semiconductor integrated circuit according to claim 7 , wherein said memory test circuit further includes:
a test access port controller configured to output test redundancy codes representing said redundancy codes, and
an input data selector configured to output said test redundancy codes as said output redundancy codes to said input data switching circuit in said redundancy memory BIST mode.
12. The semiconductor integrated circuit according to claim 7 , wherein said redundancy codes is obtained from said test result in a case where said direct memory BIST mode is performed.
13. A memory test method of testing a test target memory including an actual array portion and a redundancy portion, comprising:
outputting test data representing data for said actual array portion and said redundancy portion as output test data to said test target memory in a direct memory BIST (Built In Self Test) mode;
checking a value of read data from said test target memory with a checking expectation value to output a result of said checking as a test result in said direct memory BIST mode;
outputting first test data excluding data for said redundancy portion in said test data as input selecting data in a redundancy memory BIST mode;
outputting data obtained by adding redundancy bits to said input selecting data as said output test data to said test target memory based on said input selecting data and output redundancy codes representing redundancy codes in said redundancy memory BIST mode;
outputting data obtained by removing said redundancy bits from read data as output selecting data based on said read data from said test target memory and said output redundancy codes in said redundancy memory BIST mode; and
checking a value of said output selecting data with an expectation value for said actual array portion in said checking expectation value to output a result of said checking as said test result in said redundancy memory BIST mode.
14. The semiconductor integrated circuit according to claim 13 , wherein said redundancy codes is obtained from said test result in a case where said direct memory BIST mode is performed.