SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF

1 . A layout method for a semiconductor integrated circuit, comprising:

generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool;

generating variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance value of said variable capacitor cells, by using said automatic place and root tool; and

generating layout data of said semiconductor integrated circuit, based on said logic cell layout data and said variable capacitor cell layout data,

wherein said generating variable capacitor cell layout data comprises, arranging said control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer.

2 . The layout method for the semiconductor integrated circuit according to claim 1 , wherein said generating variable capacitor cell layout data comprises, arranging said control lines so as to be same as said signal lines in a line width.

3 . The layout method for the semiconductor integrated circuit according to claim 1 , wherein said generating variable capacitor cell layout data comprises, arranging said control lines so as to be same as said signal lines in a line pitch.

4 . The layout method for the semiconductor integrated circuit according to claim 1 , further comprising:

generating reference voltage line data by arranging power supply lines for supplying a power supply voltage to said logic cells and arranging ground lines for supplying a ground voltage to said logic cells,

wherein said generating layout data comprises, generating said layout data based on said reference voltage line data.

5 . The layout method for the semiconductor integrated circuit according to claim 4 , wherein said generating reference voltage line data comprises, arranging said power supply lines and said ground lines such that said power supply lines and said ground lines have a meshed shape, respectively.

6 . The layout method for the semiconductor integrated circuit according to claim 4 , wherein said generating variable capacitor cell layout data comprises, arranging transistors as said variable capacitor cells, and each of said transistors comprises a gate, a back gate connected to a ground terminal, a source region, and a drain region,

wherein said gate is connected to one of said power supply lines and said ground lines,

wherein said back gate is connected to the other of said power supply lines and said ground lines, and

wherein said source region and said drain region are connected to said control lines.

7 . The layout method for the semiconductor integrated circuit according to claim 4 , wherein said generating variable capacitor cell comprises:

arranging a P-channel type transistor and a N-channel type transistor as each of said variable capacitor cells; and

arranging a first control line and a second control line as said control lines,

wherein a gate of said P-channel type transistor and a back gate of said N-channel type transistor are connected to said ground lines,

wherein a gate of said N-channel type transistor and a back gate of said P-channel type transistor are connected to said power supply lines,

wherein a source and a drain of said P-channel type transistor are connected to said first control line, and

wherein a source and a drain of said N-channel type transistor are connected to said second control line.

8 . The layout method for the semiconductor integrated circuit according to claim 1 , wherein said generating variable capacitor cell layout data comprises:

arranging said variable capacitor cells;

arranging said control lines so as to be connected to said variable capacitor cells;

determining whether or not all of said variable capacitor cells are connected to said control lines; and

replacing a variable capacitor cell not connected to said control lines by a fixed capacitor cell if said variable capacitor cell not connected to said control lines exists.

9 . A computer-readable recording medium in which a computer-readable program is recorded to realize a layout method for the semiconductor integrated circuit, wherein said method comprises:

generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool;

generating variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance value of said variable capacitor cells, by using said automatic place and root tool; and

generating layout data of said semiconductor integrated circuit, based on said logic cell layout data and said variable capacitor cell layout data,

wherein said generating variable capacitor cell layout data comprises, arranging said control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer.

10 . A layout device for a semiconductor integrated circuit, comprising:

a logic cell layout section configured to generate logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool;

a variable capacitor cell layout section configured to generate variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance of said variable capacitor cells, by using said automatic place and root tool; and

a layout data generating section configured to generate layout data of the semiconductor integrated circuit, based on said logic cell layout data and said variable capacitor cell layout data,

wherein said variable capacitor cell layout section is configured to arrange said control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer.

11 . A semiconductor integrated circuit, comprising

a logic part including logic elements for realizing logic functions;

signal lines connected to said logic part;

variable capacitor cells; and

control lines configured to control capacitance of said variable capacitor cells,

wherein said signal lines are same as said control lines in a resistance of a unit length in one wiring layer.