Methods for isolating portions of a loop of pitch-multiplied material and related structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.
1. An integrated circuit, comprising:
a plurality of loops formed of semiconductor material, each loop defined by a pair of elongated portions joined at first and second opposing ends of the elongated portions, wherein all of the first ends are joined together by a first contiguous expanse of conductive material and wherein all of the second ends are joined together by a second contiguous expanse of conductive material; and
a first pair of spaced-apart transistors along each of the loops, wherein each loop forms an active area of each of the first pair of spaced-apart transistors,
wherein each of the first pair of spaced-apart transistors comprises a transistor gate, wherein each of the first ends of the loops and the transistor gates are shunted together.
2. The integrated circuit of claim 1 , wherein the first pair of spaced-apart transistors is disposed proximate the first end, wherein one of the transistors of the first pair of spaced-apart transistors is disposed along each of the elongated portions.
3. The integrated circuit of claim 2 , further comprising a second pair of transistors disposed proximate the second end, wherein one of the transistors of the second pair of transistors is disposed along each of the elongated portions.
4. The integrated circuit of claim 1 , wherein each loop forms an active area of each one of the transistors of the first pair of spaced-apart transistors.
5. The integrated circuit of claim 1 , wherein the first ends of the loops are each contiguous with an elongated expanse of semiconductor material.
6. The integrated circuit of claim 1 , wherein the semiconductor material on either side of the first pair of paced-apart transistors is doped with a dopant type opposite to that of an underlying substrate.
7. The integrated circuit of claim 6 , wherein the doped semiconductor material on either side of the first pair of paced-apart transistors constitute source/drain regions.
8. The integrated circuit of claim 1 , wherein the loops and the first pair of spaced-apart transistors constitute parts of a memory device.
9. An integrated circuit, comprising:
a plurality of spaced-apart pairs of strips of semiconductor material, wherein the plurality of spaced-apart pairs of strips of semiconductor material constitute bit lines;
a first block formed of the semiconductor material and contacting a first end of all of the pairs of strips of semiconductor material;
a first plurality of transistor gates disposed along the plurality of spaced-apart pairs of strips of semiconductor material, the first plurality of transistor gates electrically connected to the first block; and
a plurality of word lines crossing the plurality of spaced-apart pairs of strips of semiconductor material, wherein the first plurality of transistor gates are electrically connected to the wordlines by a conductive material.
10. The integrated circuit of claim 9 , further comprising:
a second block formed of the semiconductor material and contacting a second end of each of the plurality of spaced-apart pairs of strips of semiconductor material; and
a second plurality of transistor gates disposed along the plurality of spaced-apart pairs of strips of semiconductor material, the second plurality of transistor gates electrically connected to the second block of semiconductor material.
11. The integrated circuit of claim 9 , wherein the first block of the semiconductor material is on a same level as the plurality of spaced-apart pairs of strips of semiconductor material.
12. The integrated circuit of claim 11 , wherein the second block of the semiconductor material is on the same level as the plurality of spaced-apart pairs of strips of semiconductor material.
13. The integrated circuit of claim 9 , wherein the first block forms a first source/drain for a first plurality of transistors comprising the first block and the first plurality of transistor gates, and wherein the second block forms a second source/drain for a second plurality of transistors comprising the second block and the second plurality of transistor gates.
14. The integrated circuit of claim 9 , wherein the wordlines extend through the first plurality of transistor gates.
15. The integrated circuit of claim 9 , further comprising a plurality of floating gate transistors, wherein one of the floating gate transistors is disposed at intersections of the bit lines and the word lines.
16. The integrated circuit of claim 9 , wherein the plurality of spaced-apart pairs of strips of semiconductor material have a pitch of about 50 nm or less.