Nonvolatile semiconductor memory device having protection function for each memory block
View Patent ↗A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.
1. A nonvolatile semiconductor memory device comprising:
a plurality of memory blocks constituted by electrically programmable nonvolatile semiconductor memory cells;
a memory cell array constituted by the plurality of memory blocks;
an interface that communicates with an external device; and
a write circuit to write data in a selected memory block in accordance with an address and a data write command input to the interface and write a protect flag in the selected memory block in accordance with an address and a protect flag write command input to the interface, the write circuit reading the protect flag of the selected block before the data is written in the selected block, executing the write command when the protect flag has a first value, and not executing the write command when the protect flag has a second value.
2. A device according to claim 1 , wherein the protect flag is stored in a plurality of memory cells in each memory block, and when the protect flag is read, error correction is executed in accordance with a majority theory.
3. A device according to claim 1 , wherein each of said plurality of memory blocks includes a plurality of NAND-type memory units.
4. A device according to claim 3 , wherein each of said plurality of NAND-type memory units includes a plurality of memory cells connected in series.
5. A device according to claim 1 , wherein each of said plurality of memory blocks includes a plurality of pages, an erase operation is executed in units of blocks and a read/write operation is executed in units of pages.
6. A device according to claim 5 , wherein the protect flag is stored in a first page of said plurality of pages.
7. A device according to claim 1 , wherein:
each of said plurality of memory blocks includes a plurality of NAND-type memory units each including a plurality of memory cells connected in series;
each of said plurality of memory blocks includes a plurality of pages, an erase operation is executed in units of blocks, and a read/write operation is executed in units of pages; and
the protect flag is stored in a first page of said plurality of pages.
8. A device according to claim 1 , wherein
each of said plurality of memory blocks includes a plurality of pages, an erase operation is executed in units of blocks, and a read/write operation is executed in units of pages, and
the protect flag is stored in a last page of said plurality of pages.
9. A device according to claim 8 , wherein the protect flag is stored in a plurality of memory cells in each memory block, and when the protect flag is read, error correction is executed in accordance with a majority theory.
10. A device according to claim 8 , wherein each of said plurality of memory blocks includes a plurality of NAND-type memory units.
11. A device according to claim 10 , wherein each of said plurality of NAND-type memory units includes a plurality of memory cells connected in series.
12. A device according to claim 1 , wherein:
each of said plurality of memory blocks includes a plurality of NAND-type memory units each including a plurality of memory cells connected in series;
each of said plurality of memory blocks includes a plurality of pages, an erase operation is executed in units of blocks, and a read/write operation is executed in units of pages; and
the protect flag is stored in a last page of said plurality of pages.