Three-dimensional integrated circuit structure having improved power and thermal management
View Patent ↗A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.
1. A three dimensional (3D) integrated circuit (IC) structure, comprising:
at least first and second dies, each of the first and second dies having at least one power through silicon via (TSV) and one signal TSV, the at least one power TSV and one signal TSV of the first die connected to the at least one power TSV and one signal TSV of the second die, respectively; and
one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die and configured to supply power or signals to the first and/or second dies, wherein the one or more peripheral TSV structures are separate from the at least first and second dies.
2. The 3D IC structure of claim 1 , further comprising an interposer disposed between the first and the second dies.
3. The 3D IC structure of claim 1 , wherein the one or more peripheral TSV structures are disposed around the first die and/or the second die.
4. The 3D IC structure of claim 1 , wherein the one or more peripheral TSV structures supply at least power and signals.
5. The 3D IC structure of claim 1 , further comprising a third die, the third die having at least a power TSV and a signal TSV, the at least one power TSV and one signal TSV of the third die connected to the at least one power TSVs and one signal TSVs of the first and/or second dies, respectively.
6. The 3D IC structure of claim 5 , further comprising one or more peripheral TSV structures disposed adjacent to a side of the third die.
7. The 3D IC structure of claim 6 , wherein a number of peripheral TSV structures adjacent to the third die is different from a number of peripheral TSV structures adjacent to the second die and a number of peripheral TSV structures adjacent to the first die.
8. The 3D IC structure of claim 6 , wherein a number of peripheral TSV structures adjacent to the third die is the same as a number of peripheral TSV structures adjacent to the second die and a number of peripheral TSV structures adjacent to the first die.
9. The 3D IC structure of claim 5 , wherein the one or more peripheral TSV structures are disposed around the third die.
10. The 3D IC structure of claim 5 , wherein the one or more peripheral TSV structures disposed adjacent to a side of the third die supplies power.
11. The 3D IC structure of claim 5 , wherein the one or more peripheral TSV structures disposed adjacent to a side of the third die supplies signals.
12. The 3D IC structure of claim 5 , wherein the one or more peripheral TSV structures disposed adjacent to a side of the third die supplies at least power and signal.
13. The 3D IC structure of claim 1 , wherein a number of peripheral TSV structures adjacent to the first die is different from a number of peripheral TSV structures adjacent to the second die.
14. The 3D IC structure of claim 1 , wherein a number of peripheral TSV structures adjacent to the first die is the same as a number of peripheral TSV structures adjacent to the second die.
15. A 3D IC structure, comprising:
a first die having at least a power TSV and a signal TSV, the first die being surrounded by a plurality of peripheral TSV structures, wherein each peripheral TSV structure of the plurality of peripheral TSV structures is an individual block;
a second die having at least a power TSV and a signal TSV, the second die being surrounded by a plurality of peripheral TSV structures; and
a third die having at least a power TSV and a signal TSV, the third die being surrounded by a plurality of peripheral TSV structures,
wherein the plurality of peripheral TSV structures are configured to supply power or signals.
16. The 3D IC structure of claim 15 , further comprising an interposer disposed between the first and second dies.
17. The 3D IC structure of claim 15 , wherein the plurality of peripheral TSV structures supply at least power and signals.
18. A 3D IC structure, comprising:
a first die having at least a power TSV and a signal TSV;
one or more peripheral TSV structures disposed separate from and adjacent to one or more sides of the first die;
a second die;
a third die having at least a power TSV and a signal TSV; and
an interposer disposed between the second die and the third die,
wherein the one or more peripheral TSV structures are configured to supply power or signals.
19. The 3D IC structure of claim 18 , wherein the one or more peripheral TSV structures are disposed around the first die.
20. The 3D IC structure of claim 18 , wherein the one or more peripheral TSV structures supply at least power and signals.