Semiconductor circuit structure and method of forming the same using a capping layer

1. A semiconductor structure, comprising: an interconnect region; a material transfer region coupled to the interconnect region through a bonding interface established by a conductive bonding layer; and a capping layer sidewall portion which extends annularly around the material transfer region and covers the outer periphery of the bonding interface, the capping layer sidewall portion being adjacent to the conductive bonding layer and extending along an etched sidewall of the material transfer region, wherein the capping layer sidewall portion includes a dielectric material having a larger permittivity than the dielectric material of the interconnect region.

2. The structure of claim 1 , wherein the capping layer sidewall portion consists of a dielectric material.

3. The structure of claim 1 , wherein the interconnect region includes a conductive line which extends through a dielectric material region.

4. The structure of claim 3 , further including a support substrate which carries the interconnect region and an electronic device in communication with the conductive line.

5. The structure of claim 3 , wherein establishes the bonding interface, wherein the conductive bonding layer being is in communication with the conductive line.

6. The structure of claim 1 , wherein the bonding interface is a metal-to-semiconductor bonding interface.

7. The structure of claim 1 , wherein the capping layer sidewall portion extends adjacent to the interconnect region.

8. The structure of claim 1 , wherein the capping layer sidewall portion extends adjacent to an outer periphery of the interconnect region.

9. The structure of claim 1 , wherein the capping layer sidewall portion extends proximate to an outer periphery of the interconnect region and material transfer region.

10. The structure of claim 1 , wherein the capping layer sidewall portion covers a lip of the interconnect region.

11. A semiconductor structure, comprising: a support substrate which carries an electronic device; an interconnect region carried by the support substrate, the interconnect region including a dielectric material and a conductive line in communication with the electronic device; a conductive bonding layer coupled to the interconnect region, the conductive bonding layer being in communication with the conductive line; a material transfer region coupled to the interconnect region through the conductive bonding layer; and a capping layer sidewall portion which extends annularly around the conductive bonding layer, the capping layer sidewall portion being adjacent to the conductive bonding layer and extending along an etched sidewall of the material transfer region, wherein the capping layer sidewall portion includes a dielectric material having a larger permittivity than the dielectric material of the interconnect region.

12. The structure of claim 11 , wherein the material transfer region includes a dielectric material region.

13. The structure of claim 11 , wherein the material transfer region includes a semiconductor material region.

14. The structure of claim 11 , wherein the material transfer region includes a single crystalline semiconductor material region.

15. The structure of claim 11 , wherein the material transfer region includes a stack of single crystalline semiconductor material layers.

16. The structure of claim 11 , wherein the dielectric material of the capping layer sidewall portion having a larger permittivity than the material of the material transfer region.

17. The structure of claim 11 , wherein the conductive line extends through the dielectric material of the interconnect region.