Method and structure for self aligned contact for integrated circuits
A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer.
1. A method for fabricating a high voltage integrated circuit device, the method comprising:
providing a semiconductor substrate comprising a surface region, the surface region comprising a contact region, the contact region being coupled to a source/drain region of a high voltage semiconductor device;
forming a plasma enhanced oxide layer overlying the surface region;
forming a stop layer overlying the plasma enhanced oxide layer;
forming a first contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer to expose a portion of the contact region;
forming a silicide layer overlying at least the exposed portion of the contact region to form a silicided contact region;
forming an interdielectric layer having a first thickness portion overlying the silicided contact region to fill the first contact opening and having a second thickness portion overlying the stop layer;
forming a masking layer overlying the interdielectric layer;
forming an opening in the masking layer overlying a vicinity of the silicided contact region, the opening overlapping a portion of the stop layer;
patterning the interdielectric layer to form a second opening extending through the first thickness portion to expose a portion of the silicided contact region and through the second thickness portion to expose the portion of the stop layer;
maintaining the source/drain region free from any etching damage while patterning the interdielectric layer; and
forming a contact plug layer overlying the exposed portion of the silicided contact region and the exposed portion of the stop layer, wherein the first contact opening has a width that is greater than a width of the second opening.
2. The method of claim 1 wherein the semiconductor substrate is a silicon wafer.
3. The method of claim 1 wherein the width of the second opening is 0.5 micron or less.
4. The method of claim 1 wherein the high voltage semiconductor device is associated with a voltage of 12 volts and greater.
5. The method of claim 1 wherein the high voltage semiconductor device has a channel width of 1 micron and less.
6. The method of claim 1 wherein the interdielectric layer comprises a plasma enhanced oxide.
7. The method of claim 1 wherein the plasma enhanced oxide layer has a thickness of about 200 Angstroms and less.
8. The method of claim 1 wherein the source/drain region comprises a LDD structure.
9. The method of claim 1 wherein the contact plug layer comprises polysilicon.
10. The method of claim 1 wherein the contact plug layer comprises tungsten.
11. The method of claim 1 wherein the stop layer comprises silicon nitride.
12. The method of claim 1 wherein the overlapping is caused by a mis-alignment of the opening to the silicide contact region.
13. The method of claim 1 wherein the width of the first contact opening is 1.0 micron or less.
14. The method of claim 1 wherein the silicide layer comprises a refractory metal.
15. The method of claim 1 wherein the silicide layer comprises tungsten silicide, titanium silicide, or platinum silicide.
16. The method of claim 1 wherein the stop layer comprises silicon oxynitride.