Warpage resistant semiconductor package and method for manufacturing the same
View Patent ↗A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.
1. A method for manufacturing a semiconductor package, comprising the steps of:
preparing a semiconductor chip having a first surface, a second surface facing away from the first surface, and a chip region partitioned by scribe regions;
forming through-electrodes which pass through the first surface and the second surface;
selectively etching the chip region on the second surface of the semiconductor chip and to project the through-electrodes and a warpage prevention part, corresponding to the scribe regions, from the etched second surface; and
connecting the through-electrodes, projecting from the second surface of the semiconductor chip, with the connection pads of a substrate, corresponding to the through-electrodes, using conductive members.
2. The method according to claim 1 , wherein the step of forming the through-electrodes comprises the steps of:
defining grooves which pass through bonding pads formed on the first surface and have a depth less than a thickness of the semiconductor chip; and
filling the grooves with a metal.
3. The method according to claim 2 , wherein, between the step of defining the grooves and the step of filling the grooves with the metal, the method further comprises the step of forming a metal seed layer on inner surfaces of the grooves.
4. The method according to claim 2 , wherein the step of etching the chip region to project the warpage prevention part comprises the steps of:
grinding the second surface and exposing the through-electrodes;
covering the scribe regions on the second surface using a photoresist pattern, and exposing the chip region on the second surface; and
etching the chip region on the second surface using the photoresist pattern as an etch mask.
5. The method according to claim 4 , wherein, after the step of etching the chip region on the second surface, the photoresist pattern is removed from the second surface.
6. The method according to claim 1 , wherein at least two semiconductor chips are stacked.
7. The method according to claim 6 , wherein the semiconductor chips are individually parted from each other along the scribe regions.