Wafer level chip scale package
View Patent ↗A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.
1. A semiconductor device comprising:
a semiconductor substrate;
a first insulating section disposed on a first surface of the semiconductor substrate; and
a plurality of structures
wherein each of the structures comprises:
a first conductive section disposed on the first surface of the semiconductor substrate;
a second insulating section disposed over the first insulating section;
a second conductive section disposed over the second insulating section and electrically connected to the first conductive section through an opening in the second insulating section;
a third insulating section disposed over the second conductive section; and
a terminal electrically connected to the second conductive section through an opening in the third insulating section; and;
an opening between at least one pair of adjacent structures passing through the second insulating section, thus exposing the first insulating section,
wherein the third insulating section connects the at least one pair of adjacent structures and covers the opening between the at least one pair of adjacent structures.
2. The semiconductor device of claim 1 , wherein the second insulating section of at least one of the plurality structures is contiguously formed with a corresponding second insulating section of an adjacent structure.
3. The semiconductor device of claim 1 , wherein the second insulating section of at least one of the plurality of structures is isolated from a corresponding second insulating section of an adjacent structure.
4. The semiconductor device according to claim 1 , wherein at least one of the second insulating section and the third insulating section comprises an insulating resin.