Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and reading from a memory cell, and methods of programming a memory cell
In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.
1. A method of programming a memory cell comprising a pair of opposing conductive electrodes having resistance switchable material received there-between, comprising:
applying an electric field through the resistance switchable material in a prevailingly laterally oriented direction to cause mobile dopants within the resistance switchable material to move laterally toward or away from one of opposing lateral edges of the resistance switchable material to change resistance between the pair of electrodes, the resistance switchable material retaining the changed resistance after said applied electric field is removed.
2. The method of claim 1 wherein the applying of the electric field comprises applying a voltage differential across two additional conductive electrodes received laterally of opposing sides of the pair of opposing conductive electrodes, the two additional conductive electrodes being electrically insulated from the pair of opposing conductive electrodes during the applying of the electric field.
3. The method of claim 2 wherein the two additional conductive electrodes across which said voltage differential is applied are received elevationally away from the resistance switchable material.
4. The method of claim 2 wherein the two additional conductive electrodes across which said voltage differential is applied elevationally overlap the resistance switchable material.
5. The method of claim 4 wherein the two additional conductive electrodes across which said voltage differential is applied are elevationally coincident with the resistance switchable material.
6. The method of claim 1 wherein the opposing conductive electrodes of the pair are pulled to substantially the same voltage during said applying.
7. The method of claim 6 wherein each of the pair of opposing conductive electrodes is pulled to 0V during said applying.
8. The method of claim 1 wherein no external voltage is applied to the pair of opposing conductive electrodes during said applying.
9. A method of writing to and reading from a cross point memory cell of an array of cross point memory cells comprising a plurality of word lines and a plurality of bit lines crossing the plurality of word lines, individual of the cross point memory cells comprising a different one of the crossings of the plurality of word lines and the plurality of bit lines relative to one another, the method comprising:
writing to a memory cell by applying a differential write voltage between the two immediately adjacent bit lines which are on opposing lateral sides of said memory cell; and
reading from the memory cell by applying a differential read voltage between the crossing word line and the crossing bit line of the memory cell and sensing current resulting from the applying of the read voltage.
10. The method of claim 9 wherein the two immediately adjacent bit lines are electrically insulated from the memory cell.
11. The method of claim 9 wherein the differential read voltage and the differential write voltage are different from one another.
12. The method of claim 9 wherein the individual memory cells comprise resistance switchable material received between the crossing word lines and bit lines, the writing comprising switching the resistance of the resistance switchable material between at least two different resistance states which statically remains in a programmed resistance state until programmed to a different resistance state.
13. The method of claim 12 wherein the writing comprises causing mobile dopants within the resistance switchable material to move laterally toward or away from one of opposing lateral edges of the resistance switchable material.
14. The method of claim 13 wherein the writing moves the mobile dopants toward the one lateral edge to form a conductive channel which is localized along the one lateral edge.
15. The method of claim 14 wherein the writing forms the conductive channel to be of constant lateral width between the crossing word line and bit line of the memory cell.
16. The method of claim 15 wherein the writing forms the conductive channel to be of constant conductivity per unit length of the channel between the crossing bit line and crossing word line of the memory cell.
17. The method of claim 15 wherein the writing forms the conductive channel to be more conductive per unit length of the channel more proximate the crossing bit line of the memory cell than proximate the crossing word line of the memory cell.
18. The method of claim 14 wherein the writing forms the conductive channel to be of variable lateral width between the crossing word line and bit line of the memory cell.
19. The method of claim 18 wherein the writing forms the conductive channel to be wider more proximate the crossing bit line of the memory cell than proximate the crossing word line of the memory cell.
20. The method of claim 19 wherein the writing forms the conductive channel to be of constant conductivity per unit length of the channel between the crossing bit line and crossing word line of the memory cell.
21. The method of claim 19 wherein the writing forms the conductive channel to be more conductive per unit length of the channel more proximate the crossing bit line of the memory cell than proximate the crossing word line of the memory cell.
22. The method of claim 18 wherein the writing forms the lateral width of the conductive channel to taper.
23. The method of claim 13 wherein,
the resistance switchable material comprises a conductive channel of the mobile dopants which is localized along the one lateral edge; and
the writing moves the mobile dopants away from the one lateral edge to remove the conductive channel.
24. The method of claim 9 wherein the writing is simultaneously to multiple memory cells received between said pair of immediately adjacent bit lines.
25. The method of claim 9 further comprising during the writing, applying a voltage to at least some other word lines other than the crossing word line of the memory cell and that is different from any voltage that is applied to the crossing word line.
26. The method of claim 25 wherein the applying of the voltage to at least some other word lines results in an electric field component directionally different from an electric field component resulting from applying of the differential write voltage.
27. The method of claim 25 wherein the applying of the voltage to at least some other word lines prevents other memory cells associated with the other word lines from being written to by the differential write voltage.
28. A method of writing to cross point memory cells of an array of cross point memory cells comprising a plurality of word lines and a plurality of bit lines crossing the plurality of word lines, individual of the cross point memory cells comprising a different one of the crossings of the plurality of word lines and the plurality of bit lines relative to one another, the method comprising:
writing to a memory cell by applying a differential write voltage between the two immediately adjacent bit lines which are on opposing lateral sides of said memory cell.
29. The method of claim 28 comprising simultaneously writing to multiple memory cells received between said two immediately adjacent bit lines.
30. A memory cell comprising:
first and second opposing electrodes having resistance switchable material received there-between, the resistance switchable material being capable of being repeatedly programmed to at least two different resistance states, the resistance switchable material in a lowest resistance state comprising a conductive channel localized along only one of two laterally opposing edges of the resistance switchable material and extending toward and away from the first and second electrodes.
31. A non-volatile memory array comprising:
a plurality of word lines;
a plurality of bit lines crossing the plurality of word lines; and
a plurality of memory cells individually corresponding to a different one of the crossings of the plurality of word lines and the plurality of bit lines relative to one another, the memory cells individually comprising resistance switchable material received between the word lines and the bit lines where such cross and which is capable of being repeatedly programmed to at least two different resistance states, the resistance switchable material of at least one of the memory cells comprising a conductive channel localized along only one of two laterally opposing edges of said at least one memory cell and extending toward and away from the crossing word line and bit line.
32. The memory cell of claim 30 wherein the conductive channel contacts at least one of the first and second conductive electrodes.
33. The memory cell of claim 32 wherein the conductive channel contacts each of the first and second conductive electrodes.
34. The memory cell of claim 30 wherein the resistance switchable material has a minimum elevational thickness that is at least twice as great as its minimum lateral width.
35. The memory cell of claim 30 wherein the conductive channel is of constant lateral width.
36. The memory cell of claim 35 wherein the conductive channel has constant conductivity per unit length of the channel between the first and second electrodes.
37. The memory cell of claim 35 wherein the conductive channel has greater conductivity per unit length of the channel more proximate one of the first and second electrodes than proximate the other of the first and second electrodes.
38. The memory cell of claim 30 wherein the conductive channel is of variable lateral width.
39. The memory cell of claim 38 wherein the conductive channel has constant conductivity per unit length of the channel between the first and second electrodes.
40. The memory cell of claim 38 wherein the conductive channel has greater conductivity per unit length of the channel more proximate one of the first and second electrodes than proximate the other of the first and second electrodes.
41. The memory cell of claim 38 wherein the conductive channel is narrower and more conductive proximate one of the electrodes than it is proximate the other electrode.
42. The memory cell of claim 30 comprising a cross point memory cell, one of the opposing electrodes comprising a word line extending in a first direction, the other of the opposing electrodes comprising a bit line extending in a second direction different from the first direction.
43. The memory cell of claim 42 wherein the conductive channel is wider more proximate the bit line than proximate the word line.