IP Library Patent Application 12856392
Patent Application
App. No. 12/856,392

METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY

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Quick Facts
Patent No.
US None
App. No.
12/856,392
Abstract

The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed.

Claims (64)

1 . A method of forming a memory layer in a three-dimensional memory array, the method comprising:

forming a template having a plurality of depths, wherein at least one depth corresponds to a first memory line and wherein at least one depth corresponds to a memory cell pillar;

imprinting the template into a transfer material;

curing the transfer material; and

forming a memory layer using the imprinted and cured transfer material.

2 . The method of claim 1 wherein forming the template includes forming the template from at least one of quartz and fused silica.

3 . The method of claim 1 wherein forming the template includes forming a template including a plurality of trenches corresponding to rails for a plurality of memory lines.

4 . The method of claim 1 wherein forming the template includes forming a template including a plurality of holes corresponding to pillars for a plurality of memory cells.

5 . The method of claim 1 wherein forming the template includes forming a template including a plurality of holes corresponding to pillars for a plurality of memory cells and a plurality of trenches corresponding to rails for a plurality of memory lines.

6 . The method of claim 5 wherein forming the template includes forming the holes in the trenches.

7 . The method of claim 6 wherein forming the holes in the trenches includes forming holes adapted to be used to form a pillar structure in a transfer material.

8 . The method of claim 7 wherein forming the holes in the trenches includes forming holes wherein a combined depth of the holes and trenches is greater than a depth of the trenches alone.

9 . The method of claim 1 wherein imprinting the template into a transfer material includes imprinting the template into a transfer material that includes resist.

10 . The method of claim 1 wherein imprinting the template into a transfer material includes imprinting the template to form a pattern of rails and pillars in the transfer material.

11 . The method of claim 1 wherein imprinting the template into a transfer material includes imprinting the template into a transfer material layer formed on a hardmask layer which is formed on a memory material layer which is formed on a conductive material layer.

12 . The method of claim 11 wherein imprinting the template into the transfer material layer includes imprinting the template into the transfer material layer such that at least one imprint depth reaches an area of the hardmask layer.

13 . The method of claim 12 wherein forming a memory layer using the imprinted and cured transfer material includes etching the area of the hardmask layer reached by the template.

14 . The method of claim 13 wherein forming a memory layer using the imprinted and cured transfer material includes etching the memory material layer area below the etched area of the conductive material layer.

15 . The method of claim 14 wherein forming a memory layer using the imprinted and cured transfer material includes etching the conductive material layer area below the etched area of the memory material layer.

16 . The method of claim 1 wherein imprinting the template into a transfer material includes imprinting the template into a transfer material layer formed on a memory material layer which is formed on a conductive material layer.

17 . The method of claim 16 wherein imprinting the template into the transfer material layer includes imprinting the template into the transfer material layer such that at least one imprint depth reaches an area of the memory material layer.

18 . The method of claim 17 wherein forming a memory layer using the imprinted and cured transfer material includes etching the area of memory material layer reached by the template.

19 . The method of claim 18 wherein forming a memory layer using the imprinted and cured transfer material includes etching the conductive material layer area below the etched area of the memory material layer to form memory cell pillars on conductive lines.

20 . A memory layer in a three-dimensional memory array, the memory layer comprising:

a plurality of memory lines and pillars formed by a process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the pillars; and

a plurality of memory cells formed in the pillars and operatively coupled to the memory lines.

21 . The memory layer of claim 20 wherein the imprint lithography template is formed from at least one of quartz and fused silica.

22 . The memory layer of claim 21 wherein the template includes a plurality of trenches corresponding to rails for the plurality of memory lines.

23 . The memory layer of claim 22 wherein the template includes a plurality of holes corresponding to pillars for the plurality of memory cells.

24 . The memory layer of claim 21 wherein the template includes a plurality of holes corresponding to pillars for the plurality of memory cells and a plurality of trenches corresponding to rails for the plurality of memory lines.

25 . The memory layer of claim 24 wherein the template includes the holes disposed within the trenches.

26 . The memory layer of claim 25 wherein the template includes the holes disposed in the trenches along a length of the trenches.

27 . The memory layer of claim 24 wherein the template includes the holes disposed within the trenches and having a depth greater than a depth of the trenches alone.

28 . The memory layer of claim 24 wherein the template includes a plurality of landings corresponding to contact pads.

29 . The memory layer of claim 21 wherein the template includes a plurality of holes corresponding to pillars for memory cells, a plurality of trenches corresponding to rails for memory lines, and a plurality of landings corresponding to contact pads.

30 . The memory layer of claim 29 wherein the template includes a landing at alternate opposite ends of each adjacent trench.

31 . The memory layer of claim 30 wherein the template includes features for forming vias disposed on the landings.

32 . A memory layer formed using the method of claim 1 .

33 . An imprint lithography mask for manufacturing a memory layer in a three dimensional memory, the mask comprising:

a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths,

wherein at least one imprint depth corresponds to trenches for forming memory lines and wherein at least one depth corresponds to holes for forming pillar-shaped memory cells on the memory lines.

34 . The imprint lithography mask of claim 33 wherein the imprint lithography mask is formed from at least one of quartz and fused silica.

35 . The imprint lithography mask of claim 34 wherein the mask includes a plurality of trenches for forming corresponding rails for a plurality of memory lines.

36 . The imprint lithography mask of claim 34 wherein the mask includes a plurality of holes for forming corresponding pillars for a plurality of memory cells.

37 . The imprint lithography mask of claim 34 wherein the mask includes a plurality of holes corresponding to pillars for a plurality of memory cells and a plurality of trenches corresponding to rails for a plurality of memory lines.

38 . The imprint lithography mask of claim 37 wherein the mask includes the holes disposed within the trenches.

39 . The imprint lithography mask of claim 38 wherein the holes disposed within the trenches are disposed along a length of the trenches.

40 . The imprint lithography mask of claim 39 wherein the holes disposed within the trenches have a depth greater than a depth of the trenches alone.

41 . The imprint lithography mask of claim 40 wherein the mask includes a plurality of landings corresponding to contact pads.

42 . The imprint lithography mask of claim 34 wherein the mask includes a plurality of holes corresponding to pillars for memory cells, a plurality of trenches corresponding to rails for memory lines, and a plurality of landings corresponding to contact pads.

43 . The imprint lithography mask of claim 42 wherein the mask includes a landing at alternate opposite ends of each adjacent trench.

44 . The imprint lithography mask of claim 33 wherein the mask is adapted to concurrently form memory lines and memory cells for a memory layer by imprinting the mask into a transfer material that includes resist.

45 . The imprint lithography mask of claim 33 wherein the mask is adapted to be used to form a memory layer from a layer of transfer material deposited on a memory material layer which is deposited on a conductive layer.

46 . The imprint lithography mask of claim 33 wherein the mask is adapted to be used to form a memory layer from a layer of transfer material deposited on a hardmask layer which is deposited on a memory layer which is deposited on a conductive layer.

46 . A three dimensional memory array comprising:

a plurality of horizontal memory layers formed on top of each other and electrically coupled to each other by vertical zias, the zias formed from aligned vias in each memory layer, and the memory layers including a plurality of memory lines and the memory cell pillars, both formed concurrently using an imprint lithography mask.

47 . The three dimensional memory array of claim 46 wherein the plurality of memory lines and pillars are formed by a double subtractive process using the imprint lithography mask having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the pillars.

48 . The three dimensional memory array of claim 47 wherein the imprint lithography mask is formed from at least one of quartz and fused silica.

49 . The three dimensional memory array of claim 48 wherein the imprint lithography mask includes a plurality of trenches corresponding to rails for a plurality of memory lines.

50 . The three dimensional memory array of claim 48 wherein the imprint lithography mask includes a plurality of holes corresponding to pillars for a plurality of memory cells.

51 . The three dimensional memory array of claim 48 wherein the imprint lithography mask includes a plurality of holes corresponding to pillars for a plurality of memory cells and a plurality of trenches corresponding to rails for a plurality of memory lines.

52 . The three dimensional memory array of claim 51 wherein the imprint lithography mask includes the holes disposed in the trenches.

53 . The three dimensional memory array of claim 46 wherein the memory layers are formed by imprinting the imprint lithography mask into a transfer material that includes resist.

54 . The three dimensional memory array of claim 53 wherein the memory layers are formed using a layer of transfer material deposited on a memory material layer which is deposited on a conductive layer.

Assignments (4)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038809/0672 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2010
From: SCHEUERLEIN, ROY E.; CHEN, YUNG-TIN
To: SANDISK 3D LLC
Reel/Frame 024853/0019 →