Semiconductor circuit
A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.
1. A method of forming a semiconductor circuit, comprising:
providing a carrier substrate which carries an interconnect region;
providing a donor layer coupled to a donor substrate with a detach layer;
coupling the donor layer to the carrier substrate through a metal bonding layer positioned between the donor layer and interconnect region;
decoupling the donor substrate from the detach layer so the donor layer is carried by the carrier substrate; and
forming a first electronic device with the donor layer.
2. The method of claim 1 , wherein the interconnect region includes a refractory metal.
3. The method of claim 1 , wherein the first electronic device is formed with the donor layer after the donor layer is coupled to the carrier substrate.
4. The method of claim 1 , wherein the step of coupling a donor layer to the substrate includes forming a metal bonding interface.
5. The method of claim 1 , wherein the donor layer consists essentially of a semiconductor material before the donor layer is coupled to the carrier substrate.
6. The method of claim 1 , further including forming a capacitor connected to the first electronic device.
7. The method of claim 6 , wherein the capacitor is formed after the donor layer is coupled to the substrate.
8. The method of claim 1 , wherein the first electronic device operates as a static random access memory device.
9. The method of claim 1 , wherein the first electronic device operates as a non-volatile memory device.
10. The method of claim 1 , wherein the detach layer includes porous semiconductor material.
11. The method of claim 1 , wherein the detach layer includes dielectric material.
12. A method of forming a semiconductor circuit, comprising:
providing a carrier substrate which carries an interconnect region;
providing a donor layer coupled to a donor substrate with a detach layer;
coupling the donor layer to the carrier substrate by forming a metal-to-metal bonding interface;
decoupling the donor substrate from the detach layer so the donor substrate is carried by the carrier substrate; and
forming a first electronic device with the donor layer after the bonding interface is formed.
13. The method of claim 12 , wherein the donor layer does not include a second electronic device before the bonding interface is formed.
14. The method of claim 12 , wherein the donor layer consists essentially of a semiconductor material before the bonding interface is formed.
15. The method of claim 12 , wherein a portion of the donor layer between the electronic device and bonding interface consists essentially of semiconductor material.
16. The method of claim 12 , further including forming a capacitor connected to the electronic device.
17. The method of claim 16 , wherein the capacitor is formed after the bonding interface.
18. The method of claim 16 , wherein the electronic device and capacitor operate as a dynamic random access memory cell.
19. The method of claim 12 , wherein the electronic device operates as a static random access memory device.
20. The method of claim 12 , wherein the electronic device operates as a non-volatile memory device.
21. The method of claim 12 , wherein the detach layer includes porous semiconductor material.
22. The method of claim 12 , wherein the detach layer includes dielectric material.
23. The method of claim 1 , wherein the metal bonding layer includes a metal-to-metal bonding interface.
24. The method of claim 1 , wherein the metal bonding layer is spaced from the carrier substrate by the interconnect region.
25. The method of claim 1 , wherein the interconnect region includes a metal via connected to the metal bonding layer.
26. The method of claim 1 , wherein the carrier substrate includes a second electronic device in communication with the first electronic device through an interconnect which includes metal.
27. The method of claim 26 , wherein the interconnect extends above and below the metal bonding layer.
28. The method of claim 1 , further including forming the metal bonding layer on the interconnect region.
29. The method of claim 1 , further including forming the metal bonding layer on the donor layer.
30. The method of claim 1 , wherein the metal bonding layer includes a first metal layer formed on the interconnect region and a second metal layer formed on the donor layer.
31. The method of claim 1 , wherein the step of providing the donor layer includes forming the donor layer so it has a uniform doping concentration.
32. The method of claim 1 , wherein the step of providing the donor layer includes forming the donor layer so it has a non-uniform doping concentration.
33. A method of forming a semiconductor circuit, comprising:
providing a carrier substrate which carries an interconnect region having a metal via;
providing a donor layer coupled to a donor substrate with a detach layer;
coupling the donor layer to the carrier substrate through a metal bonding layer spaced from the carrier substrate by the interconnect region; and
decoupling the donor substrate from the detach layer so the donor layer is carried by the carrier substrate.
34. The method of claim 33 , wherein the metal via includes a refractory metal.
35. The method of claim 33 , wherein the metal via and metal bonding layer are in communication with each other.
36. The method of claim 33 , wherein the metal via and metal bonding layer are connected together.
37. The method of claim 33 , wherein the detach layer includes porous semiconductor material.
38. The method of claim 33 , wherein the metal bonding layer includes a metal-to-metal bonding interface.
39. The method of claim 33 , wherein the metal bonding layer includes a first metal layer formed on the interconnect region and a second metal layer formed on the donor layer.