Delay circuit of semiconductor device
View Patent ↗A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.
1. A delay circuit of a semiconductor device, comprising:
a first delay unit configured to be supplied with a first power supply voltage independent of variation of an external voltage; and
a second delay unit having a propagation delay characteristic different from that of the first delay unit with respect to variation of a second power supply voltage,
wherein the second delay unit includes an NMOS transistor having a gate receiving the second power supply voltage, and a source and a drain connected to an output node of the first delay unit and the second power supply voltage is dependent upon the variation of an external voltage.
2. The delay circuit as recited in claim 1 , further comprising a third delay unit connected between the first delay unit and the second delay unit.
3. The delay circuit as recited in claim 1 , wherein the first delay unit has a fixed delay time.
4. The delay circuit as recited in claim 1 , wherein the second delay unit has a delay time corresponding to the second power supply voltage.
5. The delay circuit as recited in claim 1 , wherein the second delay unit propagation delay characteristic includes a delay time which increases as the second power supply voltage increases.
6. The delay circuit as recited in claim 5 , wherein a bulk terminal of the NMOS transistor is connected to the output node of the first delay unit.
7. The delay circuit as recited in claim 1 , wherein the second power supply voltage has a voltage level substantially equal to the external voltage.
8. The delay circuit as recited in claim 1 , wherein the first power supply voltage is supplied to the first delay unit constantly.