Semiconductor device
View Patent ↗A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.
1. A semiconductor device, comprising:
a second conductive-type well configured in a substrate;
a first conductive-type body region configured over the second conductive-type well;
a gate electrode which overlaps a portion of the first conductive-type body region; and
a first conductive-type channel extension region formed in the substrate and which overlaps a portion of the gate electrode,
wherein a depth of the first conductive-type channel extension region is greater than that of a second conductive-type source region, and the depth of the first conductive-type channel extension region is smaller than that of the first conductive-type body region from a top surface of the substrate.
2. The semiconductor device of claim 1 , wherein the first conductive-type channel extension region extends over both a portion of the first conductive-type body region and a portion of the second conductive-type well.
3. The semiconductor device of claim 1 , wherein an impurity doping concentration of the first conductive-type body region is higher than that of the first conductive-type channel extension region.
4. The semiconductor device of claim 1 , further including:
a first channel formed by overlap of the gate electrode and the first conductive-type body region; and
a second channel formed by overlap of the gate electrode and the first conductive-type channel extension region disposed in the substrate.
5. The semiconductor device of claim 4 , wherein a threshold voltage level of the second channel is smaller than a threshold voltage level of the first channel.
6. The semiconductor device of claim 1 , further comprising:
a device isolation layer configured in the substrate to define an active region;
a first conductive-type pickup region disposed in the first conductive-type body region;
a second conductive-type source region disposed in the first conductive-type body region on one side of the gate electrode; and
a second conductive-type drain region disposed in the second conductive-type well and spaced apart from one end of another side of the gate electrode.
7. The semiconductor device of claim 6 , wherein an area of an overlap between the first conductive-type channel extension region and the gate electrode is controlled based on a predetermined characteristic of the semiconductor device.
8. The semiconductor device of claim 6 , wherein the device isolation layer between the gate electrode and the second conductive-type drain region partially overlaps a lower portion of the gate electrode.
9. The semiconductor device of claim 1 , further comprising:
a second conductive-type buried impurity region configured under the second conductive-type well and having a higher impurity doping concentration than the second conductive-type well.
10. The semiconductor device of claim 1 , wherein a threshold voltage level of the first conductive-type channel extension region and a threshold voltage level of the first conductive-type body region are different from each other.