Method of manufacturing semiconductor device
View Patent ↗The invention provides a method of manufacturing a semiconductor device having a MOS transistor, a resistor element, etc on one semiconductor substrate, in which the number of masks and the number of manufacturing steps are decreased. In an NMOS formation region, a channel stopper layer is formed in a P type well by a first ion implantation process. Then a punch-through prevention layer is formed in the P type well by a second ion implantation process. On the other hand, in a first high resistor element formation region and a second high resistor element formation region, utilizing the first and second ion implantation processes, a resistor layer is formed in an N type well.
1. A method of manufacturing a semiconductor device comprising a first MOS transistor with a channel of a first type and a resistor element that are formed on a semiconductor substrate, the method comprising:
forming a first element isolation film isolating a first region of the semiconductor substrate on which the first MOS transistor is formed from other portions of the semiconductor substrate;
performing a first ion implantation to form a first channel stopper layer in the first region and to form at least preliminarily a resistor layer of the resistor element in a second region of the semiconductor substrate, the first channel stopper layer preventing a channel formation under the first element isolation film;
wherein, the first channel stopper layer and the preliminary resistor layer are formed simultaneously during the first ion implantation; and
performing a second ion implantation to form a first punch-through prevention layer in the first region and to add impurities to the resistor layer, the first punch-through prevention layer preventing a punch-through of the first MOS transistor;
wherein, the first punch-through prevention layer and the impurity-added resistor layer are formed simultaneously during the second ion implantation.
2. The method of claim 1 , wherein the first ion implantation process is performed so that ions penetrate the first element isolation film.
3. The method of claim 2 , wherein the second ion implantation process is performed so that ions do not penetrate the first element isolation film.
4. The method of claim 1 , further comprising forming a second MOS transistor with a channel of a second type opposite from the channel of the first type on the semiconductor substrate, the forming of the second MOS transistor comprising:
forming a second element isolation film isolating a third region of the semiconductor substrate on which the second MOS transistor is formed from other portions of the semiconductor substrate;
performing a third ion implantation to form a second channel stopper layer in the third region, the second channel stopper layer preventing a channel formation under the second element isolation film; and
performing a fourth ion implantation to form a second punch-through prevention layer in the third region, the second punch-through prevention layer preventing a punch-through of the second MOS transistor,
wherein a resistance of the resistor layer is increased by the third and fourth ion implantations.
5. The method of claim 4 , wherein the third ion implantation is performed so that ions penetrate the second element isolation film.
6. The method of claim 1 , further comprising forming a base layer of a bipolar transistor on the semiconductor substrate by utilizing the first and second ion implantations.
7. The method of claim 6 , further comprising increasing impurity concentration of a collector layer of the bipolar transistor by utilizing the third ion implantation or the fourth implantation.
8. A method of manufacturing a semiconductor device comprising a first MOS transistor with a first channel of a first conductivity type, a second MOS transistor with a second channel of a second conductivity type opposite from the first conductivity type, a first resistor element and a second resistor element that are formed on a semiconductor substrate, the method comprising:
forming a first element isolation film isolating a first region of the semiconductor substrate on which the first MOS transistor is formed from other portions of the semiconductor substrate;
forming a second element isolation film isolating a second region of the semiconductor substrate on which the second MOS transistor is formed from first other portions of the semiconductor substrate;
forming a third element isolation film isolating a third region of the semiconductor substrate on which the first resistor element is formed from second other portions of the semiconductor substrate;
forming a fourth element isolation film isolating a fourth region of the semiconductor substrate on which the second resistor element is formed from other portions of the semiconductor substrate;
implanting impurities of the first conductivity type to the semiconductor substrate so as to form a first channel stopper layer in the first region, a first resistor layer of the first resistor element in the third region and a second resistor layer of the second resistor element in the fourth region;
the first channel stopper layer preventing a channel formation under the first element isolation film;
wherein, the first channel stopper layer in the first region, the first resistor layer of the first resistor element in the third region and the second resistor layer of the second resistor element in the fourth region are formed simultaneously;
and implanting impurities of the second conductivity type to the semiconductor substrate so as to form a second channel stopper layer in the second region and so as to make a resistance of the first resistor layer higher than a resistance of the second resistor layer, the second channel stopper layer preventing a channel formation under the second element isolation film.