Method for fabricating semiconductor device

1. A method for fabricating a semiconductor device comprising:

(a) forming a pad insulating film over a semiconductor substrate;

(b) etching a predetermined region of the pad insulating film and the semiconductor substrate to form a trench defining an active region, wherein an upper portion of the active region is wider than a lower portion of the active region;

(c) forming a device isolation structure that fills the trench;

(d) removing the pad insulating film after the device isolation structure has been formed to expose the semiconductor substrate;

(e) etching the exposed semiconductor substrate using a recess gate mask as an etching mask to form a recess;

(f) forming a gate insulating film on the exposed semiconductor substrate;

(g) forming a gate conductive layer filling the recess;

(h) forming a gate hard mask layer over the gate conductive layer; and

(i) patterning the gate hard mask layer and the gate conductive layer using a gate mask as an etching mask to form a gate,

wherein step (b) includes:

(b-1) forming a first hard mask layer over the pad insulating film;

(b-2) etching a predetermined region of the first hard mask layer, the pad insulating film, and the semiconductor substrate to form a first trench defining an active region;

(b-3) forming spacers on sidewalls of the first trench;

(b-4) etching the semiconductor substrate exposed in the first trench using the first hard mask layer and the spacers as an etching mask to form a second trench; and

(b-5) etching the semiconductor substrate exposed in the second trench to form a third trench including an undercut space where a predetermined thickness of the semiconductor substrate under a storage node junction region is removed.

2. The method according to claim 1 , wherein the first hard mask layer is selected from the group consisting of an oxide film, a nitride film, a polysilicon layer, and combinations thereof.

3. The method according to claim 1 , wherein the spacer is selected from the group consisting of an oxide film, a nitride film, a polysilicon layer and combinations thereof.

4. The method according to claim 1 , wherein the etching process for the third trench in step (b-5) is performed using an isotropic etching method.

5. The method according to claim 1 , further comprising removing the first hard mask layer and the spacers.

6. The method according to claim 5 , wherein the removing process for the first hard mask layer and the spacer is performed using a wet etching method.

7. The method according to claim 1 , wherein step (e) includes:

(e-1) forming a buffer oxide film over the exposed semiconductor substrate;

(e-2) forming a planarized second hard mask layer over the buffer oxide film;

(e-3) forming a photoresist film pattern defining a recess gate region over the second hard mask layer;

(e-4) etching the second hard mask layer, the buffer oxide film, and a predetermined thickness of the semiconductor device using the photoresist film pattern using an etching mask to form a recess;

(e-5) removing the photoresist film pattern and the second hard mask layer; and

(e-6) removing the buffer oxide film.

8. The method according to claim 7 , further comprising injecting impurity ions into the semiconductor substrate to form a well and channel ion implantation region in the semiconductor substrate disposed under the buffer oxide film.

9. The method according to claim 7 , wherein the second hard mask layer is selected from the group consisting of a nitride film, a polysilicon film, a amorphous Carbon film, a SiON film, and combinations thereof.

10. The method according to claim 7 , further comprising:

forming recess sidewall spacers on sidewalls of the recess and the buffer oxide film;

etching a predetermined thickness of the semiconductor substrate exposed at the bottom of the recess using the recess sidewall spacers as an etching mask; and

removing the recess sidewall spacers.

11. The method according to claim 10 , wherein the recess sidewall spacer is a stacked structure comprising an oxide film and a nitride film.

12. The method according to claim 10 , wherein the etching process for the semiconductor substrate is performed using an isotropic etching method.

13. The method according to claim 12 , wherein in a longitudinal direction of the active region, a shape of a lower part of the recess is elliptical or circular.

14. The method according to claim 10 , wherein the removing process for the recess sidewall spacer is performed using a wet etching method.

15. A method for fabricating a semiconductor device, comprising:

(a) etching a semiconductor substrate to form a first trench defining an active region;

(b) forming a first spacer on sidewalls of the first trench;

(c) etching a bottom of the first trench to form a second trench;

(d) etching a sidewall of the second trench to form a third trench including an undercut space;

(e) forming a device isolation structure that fills the first, second and third trenches;

(f) etching the semiconductor substrate of a gate region to form a recess; and

(g) forming a gate that fills the recess.

16. The method according to claim 15 , wherein step (d) is performed using an isotropic etching method.

17. The method according to claim 15 , wherein step (f) includes:

etching the semiconductor substrate of the gate region to form a first gate recess;

forming a second spacer on a sidewall of the first gate recess; and

etching a bottom of the first gate recess to form a second gate recess wider than the first gate recess.

18. The method according to claim 17 , wherein the shape of the lower part of the second gate recess is elliptical or circular.