Low power, multi-chip diversity architecture
View Patent ↗A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source V SS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source V DD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.
1. A multi-chip antenna diversity architecture that optimizes power consumption based on channel conditions comprising:
a first receiver chip that receives a first input signal from a first antenna, said first receiver chip comprising:
a first clock phase lock loop (PLL) that generates a first digital clock;
a first crystal oscillator operatively connected to said first clock PLL;
a first tuner that amplifies said first input signal;
a first demodulator operatively connected to said first tuner, wherein said first demodulator demodulates said first input signal received from said first tuner;
a first maximum ratio combiner (MRC) operatively connected to said first demodulator;
a first power sequencer that controls said first receiver chip; and
a first Diversity State Machine (DSM) operatively connected to said first power sequencer;
a second receiver chip that receives a second input signal from a second antenna, said second receiver chip comprising:
a second clock PLL that generates a second digital clock;
a second crystal oscillator operatively connected to said second clock PLL;
a second tuner that amplifies said second input signal;
a second demodulator operatively connected to said second tuner, wherein said second demodulator demodulates said second input signal received from said second tuner;
a second MRC operatively connected to said second demodulator;
a second power sequencer; and
a second DSM operatively connected to said second power sequencer,
wherein said first receiver chip or said second receiver chip transitions a power state based on a value of at least one channel metric,
wherein said second MRC and said second crystal oscillator are disabled upon said first receiver chip being powered ON, and
wherein any of said first receiver chip and said second receiver chip is powered OFF when said value of said channel metric exceeds a predetermined threshold value.
2. The multi-chip antenna diversity architecture of claim 1 , wherein said first DSM powers down said first receiver chip when said channel conditions allow said first receiver chip to receive audio/video.
3. The multi-chip antenna diversity architecture of claim 2 , wherein said audio/video is received error free.
4. The multi-chip antenna diversity architecture of claim 1 , wherein said first power sequencer and said first DSM are in an ‘Always On’ domain.
5. The multi-chip antenna diversity architecture of claim 1 , wherein said second power sequencer and said second DSM are in an ‘Always On’ domain.
6. The multi-chip antenna diversity architecture of claim 1 , wherein said second demodulator transmits said second input signal being demodulated to said first MRC and said second MRC.
7. The multi-chip antenna diversity architecture of claim 1 , wherein digital power is removed to reduce device leakage power.
8. The multi-chip antenna diversity architecture of claim 1 , wherein said second clock PLL, said second tuner, and said second demodulator are disabled upon said first receiver chip being powered ON.
9. The multi-chip antenna diversity architecture of claim 1 , wherein said first tuner, said first demodulator, said second crystal oscillator, and said second MRC are disabled upon said second receiver chip being powered ON, and wherein said first MRC is powered ON.
10. The multi-chip antenna diversity architecture of claim 1 , wherein said channel metric comprises any of a signal-to-noise ratio (SNR), a bit error rate (BER), a packet error rate (PER), and a received signal strength indication (RSSI).
11. The multi-chip antenna diversity architecture of claim 1 , wherein said first DSM powers down said first receiver chip when said channel conditions allow said second receiver to receive audio/video.
12. The multi-chip antenna diversity architecture of claim 11 , wherein said audio/video is received error free.
13. The multi-chip antenna diversity architecture of claim 1 , wherein said first DSM powers down said second receiver chip when said channel conditions allow said first receiver chip to receive audio/video.
14. The multi-chip antenna diversity architecture of claim 13 , wherein said audio/video is received error free.
15. The multi-chip antenna diversity architecture of claim 1 , wherein said first DSM powers down said second receiver chip when said channel conditions allow said second receiver to receive audio/video.
16. The multi-chip antenna diversity architecture of claim 15 , wherein said audio/video is received error free.
17. A multi-chip antenna diversity architecture that optimizes power consumption based on channel conditions comprising:
a first receiver chip that receives a first input signal from a first antenna, said first receiver chip comprising:
a first clock phase lock loop (PLL) that generates a first digital clock;
a first crystal oscillator operatively connected to said first clock PLL;
a first tuner that amplifies said first input signal;
a first demodulator operatively connected to said first tuner, wherein said first demodulator demodulates said first input signal received from said first tuner;
a first maximum ratio combiner (MRC) operatively connected to said first demodulator;
a first power sequencer that controls said first receiver chip; and
a first Diversity State Machine (DSM) operatively connected to said first power sequencer;
a second receiver chip that receives a second input signal from a second antenna, said second receiver chip comprising:
a second clock PLL that generates a second digital clock;
a second crystal oscillator operatively connected to said second clock PLL;
a second tuner that amplifies said second input signal;
a second demodulator operatively connected to said second tuner, wherein said second demodulator demodulates said second input signal received from said second tuner;
a second MRC operatively connected to said second demodulator;
a second power sequencer; and
a second DSM operatively connected to said second power sequencer,
wherein said first receiver chip or said second receiver chip transitions a power state based on a value of at least one channel metric,
wherein said second MRC and said second crystal oscillator are disabled upon said second receiver chip being powered ON, and
wherein any of said first receiver chip and said second receiver chip is powered OFF when said value of said channel metric exceeds a predetermined threshold value.
18. The multi-chip antenna diversity architecture of claim 17 , wherein digital power is removed to reduce device leakage power.
19. The multi-chip antenna diversity architecture of claim 17 , wherein said second clock PLL, said second crystal oscillator, said second tuner, said second demodulator, and said second MRC are disabled upon said first receiver chip being powered ON.
20. The multi-chip antenna diversity architecture of claim 17 , wherein said first tuner, said first demodulator, said second crystal oscillator, and said second MRC are disabled upon said second receiver chip being powered ON, and wherein said first MRC is powered ON.