Semiconductor device and method for fabricating semiconductor device

1. A semiconductor device, comprising:

an active region configured in or over a substrate to include a first conductive-type first deep well and a second conductive-type second deep well that form a junction therebetween;

a gate electrode extending over the junction and over a portion of the first conductive-type first deep well and a portion of the second conductive-type second deep well;

a gate insulation layer interposed between the gate electrode and the substrate;

a second conductive-type source region configured in the first conductive-type first deep well on one side of the gate electrode;

a second conductive-type drain region configured in the second conductive-type second deep well on another side of the gate electrode;

a first conductive-type first impurity region configured in the first conductive-type first deep well, the first conductive-type first deep well having a greater depth than the first conductive-type first impurity region;

a device isolation layer configured over the substrate to define boundaries of the active region; and

a first conductive-type pickup region configured in the first conductive-type first impurity region, at least a portion of the device isolation layer disposed between the second conductive-type source region and the first conductive-type pickup region,

wherein the first conductive-type first impurity region has a greater depth than the portion of the device isolation layer disposed between the second conductive-type source region and the first conductive-type pick-up region and encompasses the first conductive-type pick-up region, the second conductive-type source region, and the portion of the device isolation layer disposed therebetween in a cross-sectional view, and surrounds both the first conductive-type pick-up region and the second conductive-type source region in a plan view, the first conductive-type first impurity region extending toward the junction in such a manner as to form a first overlap region in which the first conductive-type first impurity region overlaps with a portion of the gate electrode and/or a portion of the second conductive-type source region.

2. The semiconductor device of claim 1 , wherein a threshold voltage level of the semiconductor device is directly proportional to an impurity doping concentration of the active region or to a thickness of the gate insulation layer.

3. The semiconductor device of claim 2 , wherein the threshold voltage level increases with an increase in an area of the first overlap region.

4. The semiconductor device of claim 1 , wherein the first conductive-type first impurity region has an impurity doping concentration that is higher than that in the first conductive-type first deep well.

5. The semiconductor device of claim 1 , wherein the first overlap region is formed in a manner in which the first conductive-type first impurity region overlaps with a portion of the gate electrode in the active region.

6. The semiconductor device of claim 5 , wherein the first overlap region is within a positional range from the second conductive-type source region to the junction between the first conductive-type first deep well and the second conductive-type second deep well.

7. The semiconductor device of claim 5 , wherein at least one of a line width of the first overlap region and an area of the first overlap region increase gradually from the second conductive-type source region toward the second conductive-type drain region.

8. The semiconductor device of claim 1 , wherein an impurity doping concentration of the first conductive-type first impurity region within the first overlap region has a slope.

9. The semiconductor device of claim 8 , wherein the impurity doping concentration of the first conductive-type first impurity region within the first overlap region decreases gradually from the second conductive-type source region toward the second conductive-type drain region.

10. The semiconductor device of claim 1 , wherein the second conductive-type source region is formed in the first conductive-type first deep well adjacent one side edge of the gate electrode, the second conductive-type drain region being formed in the second conductive-type second deep well and being spaced apart from, and on opposite side from the second conductive-type source region, of the gate electrode.

11. The semiconductor device of claim 1 , further comprising a second conductive-type second impurity region configured in the second conductive-type second deep well to surround the second conductive-type drain region.

12. The semiconductor device of claim 11 , wherein the device isolation layer is formed through a shallow trench isolation (STI) process.

13. The semiconductor device of claim 12 , wherein at least a portion of the device isolation layer extends between the gate electrode and the second conductive-type drain region, and is partially overlapped by a portion of the gate electrode.

14. The semiconductor device of claim 1 , wherein the first conductive-type pickup region is spaced apart from the second conductive-type source region in the plan view; and the gate electrode has a greater width than the first conductive-type first impurity region in a channel width direction such that the gate electrode protrudes from both sides of the first overlap region in the plan view.