Multi-port memory device
View Patent ↗A multi-port memory device includes: a bank having a plurality of matrices; a plurality of test data input/output units where data is input/output using a test mode for detecting a defective memory cell; a plurality of ports converted into a decoding device for decoding a command/address at the test mode; a plurality of data transfer lines for transferring data between the matrices and the test data I/O units, wherein the data transfer lines is grouped into the number of matrices; and a plurality of temporary storing units included between the data transfer lines and the matrices for temporarily storing data.
1. A test method for a multi-port memory device, comprising:
transferring data from a particular test data input/output unit to a particular memory cell while decoding and transferring addresses and commands through a plurality of ports, in a write operation of a test mode for detecting a defect of a memory cell, not in a normal mode, wherein the ports are physically separated from the test data input/output unit;
transferring data from the particular memory cell to the particular test data input/output unit in a read operation of the test mode, not in the normal mode; and
detecting a defect in the data.
2. The test method of the multi-port memory device as recited in claim 1 , wherein the test data input/output unit transfers data during the test mode.
3. The test method of the multi-port memory device as recited in claim 1 , wherein the particular memory cell and the particular test data input/output unit are particularized by the same address signal.
4. The test method of the multi-port memory device as recited in claim 1 , wherein data is transferred through a data transfer line.
5. The method of claim 1 , further comprising:
temporarily storing the data transferred from the particular test data input/output unit for the write operation; and
temporarily storing the data transferred from the particular memory cell for the read operation.
6. A method for operating a multi-port memory device, comprising:
transferring commands, addresses and data through a plurality of ports to/from a plurality of memory cells in a normal mode; and
transferring data through a particular test data input/output unit to/from the particular memory cell by decoding and transferring commands and addresses through the plurality of ports, in a test mode for detecting a defect of a memory cell, wherein the particular test data input/output unit is physically separated from the ports.
7. The method of claim 6 , further comprising:
temporarily storing the data transferred through the particular test data input/output unit during the test mode.