IP Library Granted Patent US 8,193,039
Granted Patent B2
US 8,193,039 · App. 12/889,615 · Granted Jun 5, 2012

Semiconductor chip with reinforcing through-silicon-vias

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Quick Facts
Patent No.
US 8,193,039
App. No.
12/889,615
Granted
Jun 5, 2012
Kind
B2
Abstract

A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.

Claims (24)

1. A method of manufacturing, comprising:

connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip; and

connecting a second end of the first through-silicon-via to a second die seal proximate a second side of the first semiconductor chip opposite the first side.

2. The method of claim 1 , comprising electrically connecting the first die seal to ground.

3. The method of claim 1 , wherein the first semiconductor chip comprises a electrostatic discharge diode, the method comprising electrically the first die seal to the electrostatic discharge diode.

4. The method of claim 1 , comprising connecting the first end of the first through-silicon-via to a third die seal proximate the first side of the first semiconductor chip and the second end of the first through-silicon-via to a fourth die seal proximate the second side of the first semiconductor chip.

5. The method of claim 1 , comprising connecting the first end of a second through-silicon-via to a third die seal proximate the first side of the first semiconductor chip and the second end of the second through-silicon-via to a fourth die seal proximate the second side of the first semiconductor chip.

6. The method of claim 5 , comprising connecting a conductor member to adjacent surfaces of the first and second through-silicon-vias.

7. The method of claim 1 , comprising stacking a second semiconductor chip on the first semiconductor chip.

8. The method of claim 1 , comprising electrically connecting the first through-silicon-via to a continuity circuit on the first semiconductor chip.

9. The method of claim 1 , comprising traversing the first through-silicon-via through a gettering layer in the first semiconductor chip.

10. A method of manufacturing, comprising:

forming a first through-silicon-via in a first semiconductor chip, the first through-silicon-via including a first end and a second end;

forming a first die seal ohmic contact with the first end of the first through-silicon-via; and

forming a second die seal in ohmic contact with the second end of the first through-silicon-via.

11. The method of claim 10 , comprising electrically connecting the first die seal to ground.

12. The method of claim 10 , wherein the first semiconductor chip comprises an electrostatic discharge diode, the method comprising electrically the first die seal to the electrostatic discharge diode.

13. The method of claim 10 , comprising forming a third die seal on ohmic contact with the first end of the first through-silicon-via and a fourth die seal in ohmic contact with the second end of the first through-silicon-via.

14. The method of claim 10 , comprising forming a second through-silicon-via in the first semiconductor chip with a first and a second end, a third die seal in ohmic contact with the first end of the second through-silicon-via, and a fourth die seal in ohmic contact with the second end of the second through-silicon-via.

15. The method of claim 14 , comprising forming a conductor member between adjacent surfaces of the first and second through-silicon-vias.

16. The method of claim 10 , comprising stacking a second semiconductor chip on the first semiconductor chip.

17. The method of claim 10 , comprising electrically connecting the first through-silicon-via to a continuity circuit on the first semiconductor chip.

18. The method of claim 10 , comprising forming a gettering layer in the first semiconductor chip and in contact with the first through-silicon-via.

19. The method of claim 10 , wherein at least the first through-silicon-via is formed using instructions stored in a computer readable medium.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2025
From: ADVANCED MICRO DEVICES INC.
To: ONESTA IP, LLC
Reel/Frame 070909/0934 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2024
From: ATI TECHNOLOGIES ULC
To: ONESTA IP, LLC
Reel/Frame 069379/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2010
From: REFAI-AHMED, GAMAL
To: ATI TECHNOLOGIES ULC
Reel/Frame 025037/0104 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2010
From: SU, MICHAEL Z.; BLACK, BRYAN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 025037/0162 →