High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same
An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.
1. An apparatus, comprising:
a coreless mounting substrate;
an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
a die side and a land side that is parallel planar to the die side;
a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;
an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; and
a trace in the coreless mounting substrate, wherein the recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.
2. An apparatus, comprising:
a coreless mounting substrate;
an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
a die side and a land side that is parallel planar to the die side;
a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;
an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; and
a trace in the coreless mounting substrate, wherein the recess is a first recess, the apparatus further including:
a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and
wherein the first recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.
3. An apparatus, comprising:
a coreless mounting substrate;
an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
a die side and a land side that is parallel planar to the die side;
a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;
an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; and
a trace in the coreless mounting substrate, wherein the recess is a first recess, the apparatus further including:
a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;
a first chip disposed on the coreless substrate in the first recess; and
a second chip disposed on the coreless substrate in the second recess, wherein the second chip is wire-bonded to the coreless substrate.