IP Library Granted Patent US 8,159,053
Granted Patent B2
US 8,159,053 · App. 12/892,739 · Granted Apr 17, 2012

Flat leadless packages and stacked leadless package assemblies

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Quick Facts
Patent No.
US 8,159,053
App. No.
12/892,739
Granted
Apr 17, 2012
Kind
B2
Abstract

A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Claims (27)

1. A flat leadless package comprising a leadframe comprising a plurality of leads, and at least one die mounted onto the leadframe and electrically connected to at least some of said leads by an electrically conductive polymer or an electrically conductive ink.

2. The package of claim 1 , comprising a plurality of die mounted onto the leadframe.

3. The package of claim 1 wherein at least one said die is mounted die-down.

4. The package of claim 1 wherein at least one said die is mounted die-up.

5. The package of claim 2 wherein at least two of said plurality of die are mounted in a stack.

6. The package of claim 5 wherein at least one die in the stack is oriented die-up and at least one die in the stack is oriented die-down.

7. The package of claim 5 wherein the die in the stack all have the same dimensions.

8. The package of claim 5 wherein at least one die in the stack is dimensioned differently from at least one other die in the stack.

9. The package of claim 5 wherein die pads are arranged in at least one row in a margin along or adjacent at least one interconnect edge.

10. The package of claim 9 wherein an interconnect edge of a first die in the stack overlies an interconnect edge in a second die in the stack.

11. The package of claim 9 wherein an interconnect edge of a first die in a stack is offset in relation to an interconnect edge of a second die in the stack.

12. The package of claim 1 wherein the interconnect material comprises an electrically conductive polymer.

13. The package of claim 1 wherein the interconnect material comprises a polymer filled with conductive material in particle form.

14. The package of claim 1 wherein the interconnect material comprises a material selected from: a metal filled epoxy, a metal filled thermosetting polymer, a metal filled thermoplastic polymer, an electrically conductive ink.

15. The package of claim 1 wherein the interconnect material comprises a curable material.

16. The package of claim 1 wherein the interconnect material comprises a sintered electrically conductive ink.

17. The package of claim 1 wherein the interconnect material comprises a metallization plated onto a printed electroless plating catalyst.

18. A package module comprising a plurality of stacked flat leadless packages having lead ends exposed at at least one sidewall thereof, electrically connected to circuitry in an underlying support using an electrically conductive polymer or an electrically conductive ink.

19. The package module of claim 18 wherein the underlying support comprises a package substrate.

20. The package module of claim 18 wherein the underlying support comprises a printed circuit board.

21. The package module of claim 18 wherein the underlying support comprises a module leadframe.

22. The package module of claim 18 wherein the packages in a stack have the same dimensions.

23. The package module of claim 18 wherein at least one package in a stack is dimensioned differently from at least one other package in a stack.

24. The package of claim 1 , being overmolded.

25. The package of claim 1 , being encapsulated.

26. The package module of claim 18 , said package module being overmolded.

27. The package module of claim 18 , said package module being encapsulated.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2012
From: VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
To: INVENSAS CORPORATION
Reel/Frame 029458/0905 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2012
From: VERTICAL CIRCUITS, INC.
To: VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 029186/0755 →