High resolution clock signal generator
View Patent ↗A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period T P to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of T P /N seconds over a range spanning T P seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning T P seconds with a delay resolution of T P /M seconds to provide pulses of the clock signal with a timing resolution of T P /(M*N) seconds when the integers N and M are relatively prime.
1. An apparatus for generating pulses of a third pulse sequence in response to pulses of a periodic first pulse sequence having a period T P , wherein timing of each pulse of the third pulse sequence is adjustable with a resolution that is smaller than period T P , the apparatus comprising:
a first circuit for generating each pulse of a second pulse sequence in response to a separate pulse of the first pulse sequence with a first delay adjustable by first control data with a resolution of T P /N over a first range substantially wider than T P /M, wherein M and N are differing integers greater than one;
a second circuit for generating each pulse of the third pulse sequence in response to a separate pulse of the second pulse sequence with a delay adjustable by a second control data with a resolution of T P /M over a second range substantially wider than T P /N;
a programmable sequencer for varying the first control data and the second control data in response to a pulse of the first pulse sequence; and
wherein the first circuit and the second circuit each comprise a respective phase-lock controller circuit that uses the first pulse sequence as a phase reference to provide a self-calibrating delay resolution.
2. The apparatus in accordance with claim 1 wherein M and N are relatively prime.
3. The apparatus in accordance with claim 1 wherein at least one of said first and second ranges is wider than T P .
4. The apparatus in accordance with claim 1 wherein the first range is at least as wide as (1−1/N) T P and the second range is at least as wide as (1−1/M) T P .
5. The apparatus in accordance with claim 4 wherein M and N are relatively prime.
6. The apparatus in accordance with claim 1 wherein the third pulse sequence is periodic.
7. The apparatus in accordance with claim 1 wherein the first circuit comprises a plurality of first gates connected in series for generating pulses of the second pulse sequence in response to pulses of the first pulse sequence, wherein each first gate has a switching delay of T P /N.
8. The apparatus in accordance with claim 1 wherein the second circuit comprises a plurality of second gates connected in series for generating pulses of the third pulse sequence in response to pulses of the second pulse sequence, wherein each second gate has a switching delay of T P /M.
9. The apparatus in accordance with claim 8 wherein the second circuit further comprises M third gates connected in series for generating a fourth pulse sequence in delayed response to the first pulse sequence, wherein each second and third gate has a similar switching delay of T P /M set by the magnitude of a second control signal applied to all of the second and third gates.
10. The apparatus in accordance with claim 9 wherein the phase-lock controller circuit of the second circuit monitors a phase relationship between the first pulse sequence and the fourth pulse sequence and adjusts adjusting the magnitude of the first control signal so that the fourth pulse sequence is phase-locked to the first pulse sequence.
11. The apparatus in accordance with claim 1
wherein the first circuit comprises a plurality of first gates connected in series for generating pulses of the second pulse sequence in response to pulses of the first pulse sequence,
wherein the second circuit comprises a plurality of second gates connected in series for generating pulses of the third pulse sequence in response to pulses of the second pulse sequence,
wherein each first gate has a switching delay of T P /N, and wherein each second gate has a switching delay of T P /M.
12. The apparatus in accordance with claim 11 wherein the second circuit further comprises M third gates connected in series for generating a fourth pulse sequence in delayed response to the first pulse sequence, and
wherein each second and third gate has a similar switching delay of T P /M set by the magnitude of a second control signal applied to all of the second and third gates.
13. The apparatus in accordance with claim 12 wherein the phase-lock controller circuit of the second circuit monitors a phase relationship between the first pulse sequence and the fourth pulse sequence and adjusts the magnitude of the second control signal so that the fourth pulse sequence is phase-locked to the first pulse sequence.
14. The apparatus in accordance with claim 13
wherein said plurality of first gates includes N first gates connected in series and delaying the first pulse sequence to produce a fifth pulse sequence,
wherein the switching delay of each of said first gates is controlled by a magnitude of the first control signal supplied as input thereto, and
wherein the phase-lock controller circuit of the first circuit monitors the first pulse sequence and the fifth pulse sequence and adjusts the magnitude of the first control signal so that the fifth pulse sequence is phase-locked to the first pulse sequence.
15. An apparatus for generating pulses of a third pulse sequence in response to pulses of a periodic first pulse sequence having a period T P , wherein timing of each pulse of the third pulse sequence is adjustable with a resolution that is smaller than T P , the apparatus comprising:
a first circuit for generating each pulse of a second pulse sequence in response to a separate pulse of the first pulse sequence with a delay adjustable by first control data with a resolution of T P /N;
a second circuit for generating each pulse of the third pulse sequence in response to a separate pulse of the second pulse sequence with a delay adjustable by a second control data with a resolution of T P /M;
a programmable sequencer for varying the first control data and the second control data in response to a pulse of the first pulse sequence;
wherein M and N are relatively prime integers greater than one;
and wherein the first circuit and the second circuit each comprise a respective phase-lock controller circuit that uses the first pulse sequence as a phase reference to provide a self-calibrating delay resolution.
16. The apparatus in accordance with claim 15
wherein the first circuit comprises a plurality of first gates connected in series for generating pulses of the second pulse sequence in response to pulses of the first pulse sequence,
wherein the second circuit comprises a plurality of second gates connected in series for generating pulses of the third pulse sequence in response to pulses of the second pulse sequence,
wherein each first gate has a switching delay of T P /N, and wherein each second gate has a switching delay of T P /M.
17. The apparatus in accordance with claim 16 wherein the second means further comprises M third gates connected in series for generating a fourth pulse sequence in delayed response to the first pulse sequence, and
wherein each second and third gate has a similar switching delay of T P /M set by the magnitude of a second control signal applied to all of the second and third gates.
18. The apparatus in accordance with claim 17 wherein the phase-lock controller circuit of the second circuit monitors the first pulse sequence and the fourth pulse sequence and adjusts the magnitude of the second control signal so that the fourth pulse sequence is phase-locked to the first pulse sequence.
19. The apparatus in accordance with claim 18
wherein said plurality of first gates comprises N first gates connected in series and delaying the first pulse sequence to produce a fifth pulse sequence,
wherein the switching delay of each of said first gates is controlled by a magnitude of a first control signal supplied as input thereto, and
wherein the phase-lock controller circuit of the first circuit monitors a phase relationship between the first pulse sequence and the fifth pulse sequence and adjusts the magnitude of the first control signal so that the fifth pulse sequence is phase-locked to the first pulse sequence.
20. A method for generating pulses of a third pulse sequence in response to pulses of a periodic first pulse sequence having a period T P , wherein timing of each pulse of the third pulse sequence is adjustable with a resolution that is smaller than a period T P , the method comprising the steps of:
generating each pulse of a second pulse sequence in response to a separate pulse of the first pulse sequence with a first delay adjustable by first control data with a resolution of T P /N over a first range substantially wider than T P /M, wherein M and N are differing integers greater than one;
generating each pulse of the third pulse sequence in response to a separate pulse of the second pulse sequence with a delay adjustable by a second control data with a resolution of T P /M over a second range substantially wider than T P /N; and
varying the first control data and the second control data in response to a pulse of the first pulse sequence; and
and using the first pulse sequence as a phase reference signal to provide a self-calibrating delay resolution for the first and second circuits.