Non-volatile programmable memory cell and array for programmable logic array
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
1. A non-volatile programmable memory cell formed in a semiconductor substrate of a first conductivity type and comprising:
a non-volatile MOS transistor of a second conductivity type formed in a first semiconductor region of the first conductivity type and coupled between a first power supply potential and an output node;
a volatile MOS transistor of the first conductivity type formed in a semiconductor region of the second conductivity type and coupled between the output node and a second power supply potential; and
a volatile MOS switch transistor of the second conductivity type formed in a second semiconductor region of the first conductivity type, the second semiconductor region of the first conductivity type electrically isolated from the first region of the first conductivity type, the volatile MOS switch transistor having a gate coupled to the output node through a resistor.
2. The non-volatile programmable memory cell of claim 1 wherein said first semiconductor region of the first conductivity type is a well region of the first conductivity type formed within a first well region of the second conductivity type and the second semiconductor region of the first conductivity type is the semiconductor substrate.
3. The non-volatile programmable memory cell of claim 2 wherein the volatile MOS transistor of the first conductivity type is formed in the first well region of the second conductivity type.
4. The non-volatile programmable memory cell of claim 1 wherein said first semiconductor region of the first conductivity type is a first well region of the first conductivity type formed within a well region of the second conductivity type and the second semiconductor region of the first conductivity type is a second well region of the first conductivity type is isolated from the first well region of the first conductivity type.
5. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a floating gate transistor.
6. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a flash transistor.
7. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a floating charge-trapping transistor.
8. The non-volatile programmable memory cell of claim 1 wherein said non-volatile MOS transistor is a nano-crystal transistor.
9. The non-volatile programmable memory cell of claim 1 wherein said first conductivity type is N and said second conductivity type is P.
10. The non-volatile programmable memory cell of claim 1 wherein said first conductivity type is P and said second conductivity type is N.
11. The non-volatile programmable memory cell of claim 1 wherein the volatile MOS switch transistor has a lower breakdown voltage than the non-volatile MOS transistor.
12. The non-volatile programmable memory cell of claim 1 further comprising at least one additional volatile MOS switch transistor having a gate coupled to the output node through the resistor.
13. The non-volatile programmable memory cell of claim 1 wherein the volatile MOS switch transistor having a first source/drain terminal coupled to a driven output node of a logic circuit and a second source/drain terminal coupled to a passive input node of the logic circuit, the memory cell further comprising a preset transistor coupled between the first source/drain terminal and ground, the preset transistor having a gate coupled to a circuit node biased to turn the preset transistor on when the memory cell is being erased.
14. The non-volatile programmable memory cell of claim 13 , further including a level restorer circuit coupled to the second source/drain terminal of the volatile switch transistor.