Vertical junction field effect transistors having sloped sidewalls and methods of making
View Patent ↗Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
1. A method comprising:
implanting ions into a channel layer of a semiconductor material of a first conductivity type to form implanted gate regions of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel layer is on an upper surface of a substrate layer and wherein the channel layer comprises one or more raised regions comprising an upper surface and first and second sidewalls separated by a lower surface, wherein the first and second sidewalls of the raised regions are tapered inward and form a first angle adjacent the lower surface and a second angle adjacent the upper surface, wherein the first angle is at least 5° from vertical to the upper surface of the substrate layer and wherein the second angle is <5° from vertical to the upper surface of the substrate layer, wherein the implanted gate regions are formed in the sidewalls and in the lower surface of the channel layer; and
forming a source layer of a semiconductor material of the first conductivity type on the upper surfaces of the one or more raised regions;
wherein the first and second sidewalls adjacent the lower surface of the channel layer are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer for at least half of the distance between a lower surface of the gate region proximate the substrate layer and the upper surface of the raised regions.
2. The method of claim 1 , wherein the ions are implanted into the channel layer at an angle of +/−2° from vertical to the upper surface of the substrate.
3. The method of claim 1 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <2° from vertical to the upper surface of the substrate layer.
4. The method of claim 1 , further comprising a drift layer of a semiconductor material of the first conductivity type between the substrate and the channel layer.
5. The method of claim 4 , further comprising a buffer layer between the substrate and the drift layer.
6. The method of claim 1 , further comprising a buffer layer between the substrate and the channel layer.
7. The method of claim 1 , wherein the device comprises a plurality of raised regions, wherein the plurality of raised regions are elongate and are arranged in spaced relationship as fingers.
8. The method of claim 1 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material.
9. The method of claim 1 , further comprising:
forming a gate contact on the lower surface of the channel layer;
forming a source contact on the source layer; and
forming a drain contact on the substrate layer opposite the channel layer.
10. A method comprising:
implanting ions into a channel layer of a semiconductor material of a first conductivity type to form implanted gate regions of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel layer is on an upper surface of a substrate layer and wherein the channel layer comprises a plurality of raised regions comprising an upper surface and first and second sidewalls separated by a lower surface, wherein the raised regions are elongate and are arranged in spaced relationship as fingers and wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate, wherein the implanted gate regions are formed in the sidewalls and in the lower surface of the channel layer; and
forming a source layer of a semiconductor material of the first conductivity type on the upper surfaces of the raised regions;
wherein the first and second sidewalls adjacent the lower surface of the channel layer are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer for at least half of the distance between a lower surface of the gate region proximate the substrate layer and the upper surface of the raised regions.
11. The method of claim 10 , wherein the ions are implanted into the channel layer at an angle of +/−2° from vertical to the upper surface of the substrate.
12. The method of claim 10 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <5° from vertical to the upper surface of the substrate layer.
13. The method of claim 10 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <2° from vertical to the upper surface of the substrate layer.
14. The method of claim 10 , further comprising a drift layer of a semiconductor material of the first conductivity type between the substrate and the channel layer.
15. The method of claim 14 , further comprising a buffer layer between the substrate and the drift layer.
16. The method of claim 10 , further comprising a buffer layer between the substrate and the channel layer.
17. The method of claim 10 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material.
18. The method of claim 10 , further comprising:
forming a gate contact on the lower surface of the channel layer;
forming a source contact on the source layer; and
forming a drain contact on the substrate layer opposite the channel layer.