IP Library Granted Patent US 8,003,465
Granted Patent B2
US 8,003,465 · App. 12/902,812 · Granted Aug 23, 2011

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 8,003,465
App. No.
12/902,812
Granted
Aug 23, 2011
Kind
B2
Abstract

A semiconductor device manufacturing method may include the following processes. A semiconductor substrate is partially removed using a first insulating film having first and second portions as a mask to form first and second pillars of the semiconductor substrate. A second insulating film is formed on side surfaces of the first and second pillars. A silicon film is formed on the first and second insulating films. A first part of the silicon film, which is on upper surfaces of the first and second portions, is removed. A coating film, which covers the upper surfaces of the first and second portions, is formed over the semiconductor substrate. The coating film is partially removed to expose the first insulating film and a second part of the silicon film. The second part is on side surfaces of the first and second portions. The second part is removed by dry etching.

Claims (37)

1. A method of manufacturing a semiconductor device, comprising:

forming a first insulating film on a semiconductor substrate, the first insulating film having first and second portions;

removing a part of the semiconductor substrate by using the first insulating film as an etching mask to form first and second pillars of the semiconductor substrate;

forming a second insulating film on side surfaces of the first and second pillars;

forming a silicon film on the first insulating film and the second insulating film, the silicon film facing to the side surfaces of the first and second pillars with an intervention of the second insulating film therebetween;

removing a first part of the silicon film, the first part of the silicon film being located on upper surfaces of the first and second portions of the first insulating film;

forming a coating film over the semiconductor substrate, the coating film covering the upper surfaces of the first and second portions of the first insulating film;

removing a part of the coating film to expose the first insulating film and a second part of the silicon film, the second part of the silicon film being located on side surfaces of the first and second portions of the first insulating film; and

removing the second part of the silicon film by dry etching.

2. The method according to claim 1 , further comprising:

before removing the first part of the silicon film, introducing p-type impurity into the silicon film disposed over the side surface of the first pillar to form a p-type silicon film, and introducing n-type impurity into the silicon film disposed over the side surface of the second pillar to form an n-type silicon film.

3. The method according to claim 2 , wherein removing the first part of the silicon film is performed by dry etching of a first condition, the first condition being set to have a different etching rate between the silicon film and the second insulating film, an etching speed of the silicon film being faster than an etching speed of the second insulating film under the first condition.

4. The method according to claim 3 , wherein the first condition is set to have a different etching rate between the p-type silicon film and the n-type silicon film, an etching speed of the n-type silicon film being faster than an etching speed of the p-type silicon film under the first condition.

5. The method according to claim 4 , wherein the first condition is set to use a gas including chlorine.

6. The method according to claim 1 , wherein the coating film is formed by spinning technique using an organic material.

7. The method according to claim 6 , wherein removing the second part of the silicon film is performed by dry etching of a second condition, the second condition being set to have a different etching rate between the silicon film and the coating film, an etching speed of the silicon film being faster than an etching speed of the second insulating film under the second condition.

8. The method according to claim 6 , wherein the second condition is set to use a gas including fluorine.

9. The method according to claim 7 , wherein removing a part of the coating film is performed by dry etching using a gas including oxygen.

10. The method according to claim 7 , further comprising:

after removing the second part of the silicon film, removing the coating film by an ashing process using a gas including oxygen.

11. The method according to claim 10 , wherein the first insulating film is formed by a silicon nitride film.

12. The method according to claim 11 , further comprising:

removing the coating film, the first insulating film is removed by wet etching process using heated phosphoric acid.

13. A method of manufacturing a semiconductor device, comprising:

forming a first insulating film on a semiconductor substrate, the first insulating film having first and second portions;

removing a part of the semiconductor substrate by using the first insulating film as an etching mask to form first and second pillars of the semiconductor substrate;

forming a second insulating film on side surfaces of the first and second pillars;

forming a silicon film on the first insulating film and the second insulating film, the silicon film facing to the side surfaces of the first and second pillars with an intervention of the second insulating film therebetween;

introducing p-type impurity into the silicon film disposed over the side surface of the first pillar to form a p-type silicon film;

introducing n-type impurity into the silicon film disposed over the side surface of the second pillar to form an n-type silicon film;

removing a first part of the silicon film by dry etching using a gas including chlorine, the first part of the silicon film being located on upper surfaces of the first and second portions of the first insulating film;

forming a coating film over the semiconductor substrate, the coating film covering the upper surfaces of the first and second portions of the first insulating film;

removing a part of the coating film to expose the first insulating film and a second part of the silicon film, the second part of the silicon film being located on side surfaces of the first and second portions of the first insulating film; and

removing the second part of the silicon film by dry etching using a gas including fluorine.

14. The method according to claim 13 , further comprising:

after removing the second part of the silicon film, removing the coating film and the first insulating film; and

forming a PMOS transistor by using the first pillar as a channel region of the PMOS transistor, and forming an NMOS transistor by using the second pillar as a channel region of the NMOS transistor.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →