Semiconductor device having hierarchical data line structure and control method thereof
View Patent ↗To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and supplies a potential of a VPERI level to the gate electrode when causing the switch transistor to be a non-conductive state. According to the present invention, because a potential of the gate electrode is not decreased to a VSS level when causing the switch transistor to be a non-conductive state, it is possible to reduce a current required to charge and discharge a gate capacitance of the switch transistor. Furthermore, because the VPP level is supplied to the gate electrode when causing the switch transistor to be a conduction state, a level of a signal after transfer never drops down by the amount of the threshold voltage.
1. A semiconductor device comprising:
a main data line on which data having an amplitude between a first potential and a second potential are transferred;
a sub-data line on which data having an amplitude between the first potential and the second potential are transferred;
a switch transistor provided between the sub-data line and the main data line;
a precharge circuit that precharges at least one of the sub-data line and the main data line to the second potential; and
a control unit that supplies a third potential to a control electrode of the switch transistor so as to bring the switch transistor into a conductive state and supplies a fifth potential to the control electrode so as to bring the switch transistor into a non-conductive state, wherein
a potential difference between the first and third potentials is larger than a potential difference between the first and second potentials,
a potential difference between the first and fifth potentials is smaller than a potential difference between the first potential and a fourth potential, and
a potential difference between the fourth potential and a potential of one of the sub-data line and the main data line defines a threshold voltage of the switch transistor.
2. The semiconductor device as claimed in claim 1 , further comprising an assist amplifier that drives the sub-data line to the first potential.
3. The semiconductor device as claimed in claim 2 , wherein the assist amplifier includes an assist transistor having a same conductivity type as the switch transistor.
4. The semiconductor device as claimed in claim 3 , wherein both the assist transistor and the switch transistor are N-channel MOS transistors.
5. The semiconductor device as claimed in claim 4 , wherein a thickness of a gate insulation film of the switch transistor is larger than a thickness of a gate insulation film of the assist transistor.
6. The semiconductor device as claimed in claim 2 , further comprising:
an external power source terminal to which an external power potential is supplied;
a first internal power generating circuit that receives the external power potential and generates the second potential; and
a second internal power generating circuit that receives the external power potential and generates the third potential, wherein
the second potential is equal to or lower than the external power potential, and
the third potential is higher than the external power potential.
7. The semiconductor device as claimed in claim 5 , wherein the second potential and the fifth potential have substantially a same level.
8. The semiconductor device as claimed in claim 2 , further comprising:
a plurality of memory cell arrays laid out in a matrix form;
a plurality of sense amplifiers and a plurality of column switches arranged between memory cell arrays adjacent to each other in a first direction; and
a plurality of word drivers arranged between memory cell arrays adjacent to each other in a second direction, wherein
each of the memory cell arrays includes a plurality of word lines connected to an associated one of the word drivers, a plurality of bit lines connected to an associated one of the sense amplifiers, and a plurality of memory cells each connected to an associated one of the word lines and an associated one of the bit lines, and
each of the column switches is connected between an associated one of the sense amplifiers and the sub-data line.
9. The semiconductor device as claimed in claim 8 , wherein the sub-data line extends in the second direction.
10. The semiconductor device as claimed in claim 9 , wherein the main data line extends in the first direction.
11. The semiconductor device as claimed in claim 8 , wherein the switch transistor and the assist amplifier are arranged at an intersection of the word drivers extending in a first direction with the sense amplifiers and the column switches extending in a second direction.
12. The semiconductor device as claimed in claim 8 , further comprising a data amplifier circuit that drives the main data line, wherein
the memory cell arrays, the sense amplifiers, the column switches, and the word drivers are arranged in a memory cell area, and
the data amplifier circuit and the precharge circuit are arranged being adjacent to each other in an area outside the memory cell area.
13. The semiconductor device as claimed in claim 8 , wherein when transferring the data from the sub-data line to the main data line, the control unit supplies the fifth potential to the control electrode in a first period, and supplies the third potential to the control electrode in a second period that follows the first period.
14. The semiconductor device as claimed in claim 13 , wherein the column switch turns on in the first period.
15. The semiconductor device as claimed in claim 13 , wherein the assist amplifier is brought into an activated state in the first period.
16. The semiconductor device as claimed in claim 13 , wherein the control unit supplies the third potential to the control electrode in a third period which is just before the first period.
17. The semiconductor device as claimed in claim 16 , wherein the control unit supplies the first potential to the control electrode in periods just before the third period and just after the second period.
18. The semiconductor device as claimed in claim 8 , wherein the control unit fixes a potential to be supplied to the control electrode to the third potential when transferring the data from the main data line to the sub-data line.
19. A method of controlling a semiconductor device comprising:
providing the semiconductor device having a hierarchical data line structure performing transfer of data having an amplitude between a first potential and a second potential by controlling a switch transistor connected between a sub-data line and a main data line;
supplying a third potential to a control electrode of the switch transistor, a potential difference between the first and third potentials being larger than a potential difference between the first and second potentials;
supplying a fifth potential to the control electrode after the supplying the third potential, a potential difference between the first and fifth potentials being smaller than a potential difference between the first potential and a fourth potential, and a potential difference between the fourth potential and a potential of one of the sub-data line and the main data line defining a threshold voltage of the switch transistor; and
supplying the third potential again to the control electrode after the supplying the fifth potential.