Granted Patent B2

US 8,385,139 · App. 12/923,248 · Granted Feb 26, 2013

Abstract

Claims (49)

1. A semiconductor device comprising:

an input buffer that receives an address signal having a first amplitude;

a first level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude;

an address controller that receives the address signal output from the first level shifter;

an address decoder that generates a decode signal by decoding the address signal output from the address controller; and

a second level shifter that converts an amplitude of the address signal output from the address controller or of the decode signal output from the address decoder from the second amplitude to the first amplitude such that at least an amplitude of the decode signal becomes the first amplitude.

2. The semiconductor device as claimed in claim 1 , wherein

the address signal includes a column address signal,

the address controller includes a column address controller that receives the column address signal,

the address decoder includes a column decoder that decodes the column address signal to generate a column selection signal, and

the column selection signal is supplied to a control electrode of a column switch that selects a bit line.

3. The semiconductor device as claimed in claim 2 , wherein the second level shifter is provided between the column address controller and the column decoder, and converts an amplitude of the column address signal output from the column address controller from the second amplitude to the first amplitude.

4. The semiconductor device as claimed in claim 2 , wherein the second level shifter is provided between the column decoder and the column switch, and converts an amplitude of the column selection signal from the second amplitude to the first amplitude.

5. The semiconductor device as claimed in claim 2 , further comprising a sense amplifier connected to the bit line, wherein

the sense amplifier drives the bit line in an amplitude smaller than the second amplitude.

6. The semiconductor device as claimed in claim 1 , wherein

the address signal includes a row address signal,

the address controller includes a row address controller that receives the row address signal, and

the address decoder includes a row decoder that decodes the row address signal to generate a row decode signal, wherein

the semiconductor device further comprises:

a word driver that selects a word line based on the row decode signal; and

a third level shifter that converts an amplitude of the row decode signal output from the row decoder or of an output signal of the word driver from the first amplitude to a third amplitude such that at least an amplitude level of an output signal of the word driver becomes the third amplitude that is larger than the first amplitude.

7. The semiconductor device as claimed in claim 6 , further comprising:

a sense amplifier connected to a bit line; and

a sense amplifier driver that supplies an operation voltage to the sense amplifier based on the row decode signal.

8. The semiconductor device as claimed in claim 7 , wherein

the sense amplifier driver includes a first driver that supplies a first power source potential to the sense amplifier and a second driver that supplies a second power source potential to the sense amplifier,

the row decode signal having the first amplitude is supplied to a control electrode of the first driver, and

the row decode signal having the third amplitude is supplied to a control electrode of the second driver.

9. The semiconductor device as claimed in claim 8 , wherein a potential difference between the first power source potential and the second power source potential is smaller than the second amplitude.

10. A semiconductor device comprising:

an address terminal supplied with an address signal, the address signal changing between first and second potential levels;

an internal address circuit coupled to the address terminal to receive the address signal and outputting an internal address signal, the internal address signal changing between the first potential level and a third potential level, the third potential level being lower than the second potential level; and

an address decoder coupled to the internal address circuit to receive the internal address signal and outputting a decoded signal, the decoded signal changing between the first level and a fourth potential level, the fourth potential level being higher than the third potential level.

11. The device as claimed in claim 10 , wherein the second potential level is substantially equal to the fourth potential level.

12. The device as claimed in claim 10 , wherein the address decoder comprises a first level shifter shifting a level of the internal address signal to produce an intermediate address signal that changes between the first and fourth potential levels, and a column decoder coupled to the first level shifter to receive the intermediate address signal, the address decoder further comprises column address decoder operating on the fourth potential level to produce a column address decoded signal as the decoded signal changing between the first and fourth potential levels.

13. The device as claimed in claim 10 , wherein the address decoder comprises a column address decoder decoding the internal address signal, the column decoder operating on the third potential level to produce an intermediate decoded signal that changes between the first and third potential levels, and the address decoder further comprises a second level shifter coupled to the column address decoder to receive the intermediate decoded signal and shifting a level of the intermediate decoded signal to produce a column address decoded signal as the decoded signal changing between the first and fourth potential levels.

14. The device as claimed in claim 10 , wherein the address decoder comprises a third level shifter shifting a level of the internal address signal to produce an intermediate address signal that changes between the first and fourth potential levels, and a row address decoder coupled to the third level shifter to receive the intermediate address signal, the row address decoder operating on the fourth potential level to output a row address decoded signal as the decoded signal changing between the first and fourth potential levels.

15. The device as claimed in claim 10 , wherein the address decoder a row address decoder decoding the internal address signal, the row address decoder operating on the third potential level to produce an intermediate decoded signal that changed between the first and third potential levels, and the address decoder further comprises a fourth level shifter coupled to the row address decoder to receive the intermediate decoded signal and shifting a level of the intermediated decided signal to produce a row address decoded signal as the decoded signal changing between the first and fourth potential levels.

16. A semiconductor device comprising:

a set of address terminals supplied with a set of address signals including row address information and column address information, each of the address signals changing between first and second potential levels;

an internal address circuit coupled to the set of address terminals to receive the set of address signals and outputting a set of internal address signals including row address information and column address information, each of the internal address signals changing between the first potential level and a third potential level, the third potential level being lower than the second potential level;

a row address circuit coupled to the internal address circuit to receive the row address information of the set of internal address signals and outputting a set of row address decoded signals; and

a column address circuit coupled to the internal address circuit to receive the column address information of the set of the internal address signals and outputting a set of column address decoded signals;

at least one of the row address circuit and the column address circuit changing an associated one of the set of the row address decoded signals and the set of the column address decoded signals between the first potential level and a fourth potential level that is substantially equal to the second potential level.

17. The device as claimed in claim 16 , wherein the at least one of the row address circuit and the column address circuit comprises a first level shifter shifting a level of the set of the internal address signals and outputting a set of intermediate address signals each changing between the first and fourth potential levels, and the at least one of the row address circuit and the column address circuit further comprises an address decoder operating on the fourth potential level to decode the set of internal address signals and outputting the associated one of the set of the row address decoded signals and the set of the column address decoded signals that changes between the first and fourth potential levels.

18. The device as claimed in claim 16 , wherein the at least one of the row address circuit and the column address circuit comprises an address decoder operating on the second potential level to decode the set of internal address signals and outputting a set of intermediate decoded signals changing between the first and second potential levels, and the at least one of the row address circuit and the column address circuit further comprises a second level shifter shifting a level of the set of the intermediate decoded signals and outputting the associated one of the set of the row address decoded signals and the set of the column address decoded signals.

19. The device as claimed in claim 16 , wherein the row address circuit changes the set of the row address decoded signals between the first and fourth potential levels and the column address circuit changes the set of the column address decoded signals between the first and fourth potential levels.

20. The device as claimed in claim 19 , each of the row and column address circuits comprises a level shifter circuit and an decoder circuit coupled in series, one of the level shifter circuit and the decoder circuit operating on the third potential levels and the other of the level shifter circuit and the decoder circuit operating on the fourth potential levels.

Assignments (8)