IP Library Granted Patent US 8,044,507
Granted Patent B2
US 8,044,507 · App. 12/923,303 · Granted Oct 25, 2011

Sealing apparatus for semiconductor wafer, mold of sealing apparatus, and semiconductor wafer

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Quick Facts
Patent No.
US 8,044,507
App. No.
12/923,303
Granted
Oct 25, 2011
Kind
B2
Abstract

A sealing apparatus for sealing by resin a semiconductor wafer having semiconductor elements on its surface. The apparatus includes an upper mold and a tower mold having an area where the semiconductor wafer is mounted, the lower mold having an uneven surface in the area and a shock absorber under the lower mold.

Claims (12)

1. A sealing apparatus for sealing a semiconductor wafer having semiconductor elements on its surface by resin, comprising:

an upper mold; and

a lower mold having an area where the semiconductor wafer is to be mounted directly, the lower mold having an uneven surface in the area,

wherein the uneven surface has a roughness in a range between 8 μm and 12 μm,

wherein the lower mold has a first area on which the semiconductor wafer is to be mounted, such that the entire first area is covered by a lower surface of the semiconductor wafer, and the lower surface of the semiconductor wafer has an equal area to the first area, the first area including a second area and a third area, the uneven surface of the lower mold is formed within the second area, and the uneven surface is not formed in the third area by which the second area is surrounded, and

wherein the second area is smaller than the area of the lower surface of the semiconductor wafer.

2. A semiconductor device manufacturing mold for setting a semiconductor wafer having semiconductor elements on its surface in order to seal the surface by resin, comprising:

an upper mold; and

a lower mold having an area where the semiconductor wafer is to be mounted directly, the lower mold having an uneven surface in the area,

wherein the uneven surface has a roughness in a range between 8 μm and 12 μm,

wherein the lower mold has a first area on which the semiconductor wafer is to be mounted, such that the entire first area is covered by a lower surface of the semiconductor wafer, and the lower surface of the semiconductor wafer has an equal area to the first area, the first area including a second area and a third area, the uneven surface of the lower mold is formed within the second area, and the uneven surface is not formed in the third area by which the second area is surrounded, and

wherein the second area is smaller than the area of the lower surface of the semiconductor wafer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2014
From: MATSUMOTO, JIRO
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 033247/0948 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2014
From: MATSUMOTO, JIRO
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 033212/0095 →
CHANGE OF NAME Recorded Jun 30, 2014
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 033212/0121 →