Semiconductor device and method of manufacturing the same
View Patent ↗Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.
1. A method of manufacturing a semiconductor device, comprising:
forming a plurality of active regions and a plurality of isolation regions between adjacent active regions in a substrate,
forming a groove in each of the plurality of active regions, a bottom surface of the groove being below an upper surface of the active region; and
forming a gate structure in each of the plurality of grooves, wherein the plurality of grooves are perpendicular to the gate structure, the gate structure includes a blocking insulation layer, and a lowest surface of the blocking insulation layer is higher than the plurality of isolation regions and extends into the gate structure.
2. The method of claim 1 , wherein the plurality of grooves extend along a source, a channel, and a drain.
3. The method of claim 1 , wherein the gate structure includes a floating gate structure.
4. The method of claim 3 , wherein forming the plurality of active regions and the plurality of isolation regions further includes,
forming a mask pattern, including a pad oxide and mask nitride layer, on the substrate,
etching the substrate using the mask pattern as an etching mask to form a plurality of trenches,
filling the plurality of trenches with dielectric material to form the plurality of isolation regions,
selectively removing the mask nitride layer to expose an upper side of the pad oxide and a portion of each isolation region.
5. The method of claim 4 , wherein forming the groove in each of the plurality of active regions further includes,
forming spacers on sidewalls of each isolation region, a width of the spacer defining a width of each of the plurality of grooves,
etching the exposed pad oxide and the substrate using the spacers and the isolation regions as an etching mask to form the plurality of grooves.
6. The method of claim 4 , wherein forming the gate structure in each of the plurality of grooves further includes,
forming a tunneling insulation layer in each of the plurality of grooves,
filling each of the plurality of grooves to form a floating gate layer,
etching the spacers and an upper portion of the isolation regions and leaving a portion of the spacer on the pad oxide,
forming the blocking insulation layer on the floating gate layer,
forming a control gate layer on the blocking insulation layer
patterning the control gate layer to form the gate structure, and
implanting ions using the gate structure as an implanting mask to form impurity regions on the active regions.
7. The semiconductor device of claim 1 , wherein the gate structure is a charge trap gate structure.
8. The method of claim 7 , wherein forming the plurality of active regions and the plurality of isolation regions further includes,
forming a mask pattern, including a pad oxide and mask nitride layer, on the substrate,
etching the substrate using the mask patterns as an etching mask to form a plurality of trenches,
filling the plurality of trenches with dielectric material to form the plurality of isolation regions,
selectively removing the mask nitride layer to expose an upper side of the pad oxide and a portion of each isolation region.
9. The method of claim 8 , wherein forming the groove in each of the plurality of active regions further includes,
forming spacers on both sidewall of each isolation region, a width of the spacer defining a width of each of the plurality of grooves,
etching the exposed pad oxide and the substrate using the spacers and the isolation regions as an etching mask to form the plurality of grooves.
10. The method of claim 7 , wherein forming the gate structure in each of the plurality of grooves further includes,
forming an ONO layer in each of the plurality of grooves and on each of the plurality of isolation regions, and
forming a control gate on the ONO layer.
11. The method of claim 10 , wherein forming the ONO layer includes
forming a first oxide layer in each of the plurality of grooves and on each of the plurality of isolation regions,
forming a nitride layer on the first oxide layer, and
forming a second oxide layer on the nitride layer.
12. The method of claim 10 , wherein forming the gate structure in each of the plurality of grooves further includes
forming a tunnel insulating layer in each of the plurality of grooves and on each of the plurality of isolation regions,
forming a control gate charge storage layer on the tunnel insulating layer,
forming the blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunnel insulating layer; and
forming a gate electrode on the blocking insulating layer, wherein the gate electrode includes a metal layer.
13. The method of claim 12 , wherein the tunnel insulating layer comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride.
14. The method of claim 12 , wherein the charge storage layer comprises at least one of silicon nitride, silicon oxynitride, silicon-rich oxide, metallic oxynitride and other metallic oxide materials.
15. The method of claim 12 , wherein the blocking insulating layer comprises a metal oxide doped with a group IV element.
16. The method of claim 12 , wherein the blocking insulating layer comprises at least one of HfO 2 , Al 2 O 3 , La 2 O 3 , Hf 1-X Al X O Y , Hf X Si 1-X O 2 , Hf—Si-oxynitride, ZrO 2 , Zr X Si 1-X O 2 , and Zr—Si-oxynitride.
17. The method of claim 12 , wherein the gate electrode comprises a metal layer having a work-function of at least 4 eV.
18. The method of claim 12 , wherein metal layer is one of titanium, titanium nitride, tantalum nitride, tantalum, tungsten, hafnium, niobium, molybdenum, ruthenium dioxide, molybdenum nitride, iridium, platinum, cobalt, chrome, ruthenium monoxide, titanium aluminide (Ti 3 Al), Ti 2 AlN, palladium, tungsten nitride (WN x ), tungsten silicide (WSi), nickel silicide, or combinations thereof.
19. The method of claim 1 , wherein a shape of a bottom portion of each of the plurality of grooves has an obtuse or rounded profile.
20. The method device of claim 1 , wherein each groove is in a center portion of the active region.
21. A method of manufacturing a semiconductor device, comprising:
forming a plurality of active regions and a plurality of isolation regions between adjacent active regions in a substrate,
forming a groove in each of the plurality of active regions, a bottom surface of the groove being below an upper surface of the active region; and
forming a gate structure in each of the plurality of grooves, wherein the plurality of grooves are perpendicular to the gate structure, major axes of the active regions and major axes of the plurality of grooves are in the same direction; the gate structure includes a blocking insulation layer, and a lowest surface of the blocking insulation layer is higher the plurality of isolation regions and extends into the gate structure.
22. The method of claim 21 , wherein the plurality of grooves extend along a source, a channel, and a drain.
23. A method of manufacturing a semiconductor device, comprising:
forming a mask pattern, including a pad oxide and mask nitride layer, on a substrate;
etching the substrate using the mask pattern as an etching mask to form a plurality of trenches and a plurality of active regions therebetween;
filling the plurality of trenches with dielectric material to form a plurality of isolation regions;
selectively removing the mask nitride layer to expose an upper side of the pad oxide and a portion of each isolation region;
forming spacers on sidewalls of each isolation region, a width of the spacer defining a width of each of a plurality of grooves,
etching the exposed pad oxide and the substrate using the spacers and the isolation regions as an etching mask to form the plurality of grooves;
forming a tunneling insulation layer in each of the plurality of grooves;
filling each of the plurality of grooves to form a floating gate layer;
etching the spacers and an upper portion of the isolation regions and leaving a portion of the spacer on the pad oxide;
forming a blocking insulation layer on the floating gate layer;
forming a control gate layer on the blocking insulation layer;
patterning the control gate layer to form the gate structures; and
implanting ions using the gate structure as an implanting mask to form impurity regions on the active regions.