Semiconductor device capable of detecting defect of column selection line
View Patent ↗To include a comparison circuit that generates comparison results by comparing plural pieces of data simultaneously read via data lines with expected values, an AND gate that activates a first determination signal in response to a fact that at least one of the comparison results indicates a mismatch, and an OR gate that activates a second determination signal in response to a fact that all the comparison results indicate a mismatch. With this arrangement, when a detection test of a defective address is performed in a wafer state, a defect of a column selection line can be detected.
1. A semiconductor device comprising:
a comparison circuit that generates a plurality of comparison result signals by comparing a plurality of read data simultaneously read via a plurality of data lines with expected values, respectively;
a first determining circuit that activates a first determination signal when at least one of the comparison result signals indicates a mismatch; and
a second determining circuit that activates a second determination signal when all the comparison result signals indicate a mismatch.
2. The semiconductor device as claimed in claim 1 , wherein the second determining circuit activates the second determination signal when all the comparison result signals simultaneously indicate a mismatch.
3. The semiconductor device as claimed in claim 1 , wherein the second determining circuit activates the second determination signal when each of the comparison result signals indicates a mismatch at least once when the comparison circuit performs a plurality of comparison operations to the data lines.
4. The semiconductor device as claimed in claim 1 , further comprising a plurality of switch circuits that supply the read data to corresponding ones of the data lines, respectively,
wherein the switch circuits are controlled by a same control signal.
5. A semiconductor device comprising:
at least one word line;
a plurality of memory cells selected by the word line;
a plurality of bit lines connected to the memory cells, respectively;
a plurality of data lines;
a plurality of column switches that connect the bit lines and the data lines, respectively;
a column selection line that supplies a column selection signal in common to the column switches; and
a determining circuit that determines a defect of the column selection line by evaluating a plurality of data on the data lines by activating the word line and the column selection signal.
6. The semiconductor device as claimed in claim 5 , further comprising a comparison circuit that generates a plurality of comparison result signals that correspond to read data, respectively by comparing the read data with a plurality of expected values, respectively,
wherein the determining circuit determines a defect of the column selection line based on the comparison result signals.
7. The semiconductor device as claimed in claim 6 , wherein the determining circuit determines that the column selection line is defective when all the comparison result signals indicate a mismatch.
8. The semiconductor device as claimed iri claim 7 , wherein the determining circuit determines that the column selection line is defective when all the comparison result signals that correspond to the read data simultaneously read from the memory cells by activating the word line indicate a mismatch.
9. The semiconductor device as claimed in claim 7 , wherein a plurality of the word lines are provided, and
the determining circuit sequentially determines comparison result signals by sequentially activating a different one of the word lines, and determines that the column selection line is defective when each of the comparison result signals that corresponds to each data line indicates a mismatch at least once.
10. The semiconductor device according to claim 5 , wherein the column switches each comprise a Metal-Oxide Semiconductor (MOS) transistor.
11. The semiconductor device according to claim 10 , wherein the column selection signal is supplied on common to gate electrodes of the MOS transistors of the column switches.
12. The semiconductor device according to claim 5 , further comprising a register that stores a plurality of expected values,
wherein the determining circuit determines the defect of the column selection line based on a comparison between the expected values and the data on the data lines, respectively.
13. The semiconductor device according to claim 12 , further comprising a plurality of exclusive OR gates, each exclusive OR gate comprising:
a first input that receives the data on a data line;
a second input that receives a respective expected value from the register; and
an output that outputs a logic result to the determining circuit.
14. The semiconductor device according to claim 13 , wherein the determining circuit comprises an AND gate and an OR gate, each receiving the logic result from each exclusive OR gate.
15. The semiconductor device according to claim 14 , wherein, when the OR gate outputs a logic high, the determining circuit determines that the column selection line has the defect.
16. The semiconductor device according to claim 14 , wherein, when the AND gate outputs a logic high, the determining circuit determines that at least one of the bit lines has a defect.
17. A semiconductor device comprising:
a memory cell array including a plurality of memory cells;
a plurality of data lines electrically coupled to the memory cell array to receive a plurality of read data signals from the memory cell array, respectively;
a register temporarily storing a plurality of expected data signals;
a plurality of comparators electrically coupled to the data lines and the register to compare the read data signals with the expected data signals, respectively, each of the comparators producing a comparison signal that takes a first logic level when an associated one of the read data signals is coincident with an associated one of the expected data signals and a second logic level when the associated one of the read data signals is in coincident with the associated one of the expected data signals; and
a first logic gate coupled to the comparators to produce a first output signal that takes one of the first and second logic levels in response to each of the comparison signals taking the second logic level and takes the other of the first and second logic levels in response to at least one of the comparison signals taking the first logic level.
18. The semiconductor device as claimed in claim 17 , further comprising a second logic gate coupled to the comparators to produce a second output signal that takes the other of the first and second logic levels in response to each of the comparison signals taking the first logic level and the one of the first and second logic levels in response to at least one of the comparison signals taking the second logic level.
19. The semiconductor device as claimed in 18 , wherein the first logic gate performs a logical sum operation and the second logic gate performs a logical product operation.
20. The semiconductor device as claimed in 18 , wherein the first logic gate performs a logical product operation and the second logic gate performs a logical sum operation.