IP Library Granted Patent US 8,351,292
Granted Patent B2
US 8,351,292 · App. 12/929,327 · Granted Jan 8, 2013

Semiconductor device and data processing system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,351,292
App. No.
12/929,327
Granted
Jan 8, 2013
Kind
B2
Abstract

A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the plurality of receivers; and a second driver outputting the reference signal with an impedance higher than an impedance with which each of the first drivers outputs the small-amplitude signal. The second transmission wiring is arranged between first and second power supply wirings corresponding to first and second potentials of the small-amplitude signal. The first and second potentials are supplied to each of the first drivers. The plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings.

Claims (21)

1. A semiconductor device comprising:

a plurality of first receivers, each operating at a first operation voltage, receiving a single-ended input signal having a small amplitude, and having a function of sensing the single-ended input signal;

a plurality of first drivers, each operating at a second operation voltage lower than the first operation voltage and outputting the single-ended input signal having a first voltage difference with a first impedance value;

a plurality of first transmission wirings, each having a first length corresponding to a distance between one of the first drivers and one of the first receivers and transmitting the single-ended input signal;

a common reference signal inputted to each of the plurality of first receivers;

a second driver operating at the second operation voltage and outputting the reference signal with a second impedance value higher than the first impedance value;

a second transmission wiring having at least the first length and transmitting the reference signal; and

first and second internal power supply generation circuits, relating to the second operation voltage, generating high- and low-side potentials of the single-ended input signal, respectively, supplying the potentials to each of the plurality of first drivers, and outputting the potentials to first and second power supply wirings having at least the first length, respectively,

wherein the second transmission wiring is arranged between the first and second power supply wirings, without the plurality of first transmission wirings being arranged between the first and second power supply wirings, and

wherein the plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings.

2. The semiconductor device according to claim 1 ,

wherein the single-ended input signal has the first voltage difference represented by a first potential corresponding to a first logic level and a second potential corresponding to a second logic level, and

wherein each of the first receivers outputs a voltage having a second voltage difference that is larger than the first voltage difference and that relates to the first operation voltage.

3. The semiconductor device according to claim 1 ,

wherein each of the first receivers comprises a differential circuit having first and second differential input terminals connected to the single-ended input signal and the reference signal, respectively, and

wherein each of the first drivers is an inverter comprising first and second transistors are mutually different conductivity type and connected in series to each other.

4. The semiconductor device according to claim 3 ,

wherein the second driver comprises at least a resistive element connected to the second transmission wiring.

5. The semiconductor device according to claim 1 , further comprising:

a plurality of control signals each for performing mutual exclusion control,

wherein each of the plurality of first drivers controlled by the plurality of control signals is selectively connected to one of the first transmission wirings each corresponding to one of the first receivers.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →