Package substrate unit and method for manufacturing package substrate unit
A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.
1. A method for manufacturing a package substrate unit, the method comprising:
forming a core layer;
forming a buildup layer on the core layer;
forming in an insulation layer that is positioned on an outside of the buildup layer a hole at a position where a via is formed, and forming a conductive seed metal layer on the insulation layer and on a surface where the hole is formed;
forming the via at the position;
forming a conductive pad that is positioned on the via and the conductive seed metal layer;
forming a dry film resist layer on the conductive seed metal layer and the conductive pad;
forming in the dry film resist layer a first opening at a position of the hole, and forming a metal post by filling the first opening with copper plating;
removing the dry film resist layer;
forming a solder resist layer on the insulation layer;
forming in the solder resist layer a second opening at a surface of the conductive pad and around the metal post; and
printing a solder bump at the second opening.
2. The method according to claim 1 , wherein the solder resist layer is formed so that a height of the solder resist layer is lower than a height of the metal post.