METHOD AND STRUCTURE FOR ELECTRO-PLATING ALUMINUM SPECIES FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DISPLAYS
Method and structure for electro-plating aluminum species for top metal formation of liquid crystal on silicon displays. In a specific embodiment, the invention provides a method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., semiconductor wafer, silicon wafer, silicon on insulator. The method includes forming a transistor layer (e.g., MOS transistors) overlying the substrate. The method includes forming an interlayer dielectric layer (e.g., PSG, BPSG, FSG) overlying the transistor layer. The method includes forming a first conductive layer overlying the interlayer dielectric layer and forming a second interlayer dielectric layer overlying the first conductive layer. A dual damascene via structure is formed within the second interlayer dielectric layer. The method deposits a barrier metal layer (e.g., TiN, Ti/TiN) within the dual damascene via structure to form a liner that covers exposed regions of the dual damascene via structure.
1 . A method for fabricating a liquid crystal on silicon display device, the method comprising:
providing a substrate;
forming a transistor layer overlying the substrate;
forming an interlayer dielectric layer overlying the transistor layer;
forming a first conductive layer overlying the interlayer dielectric layer;
forming a second interlayer dielectric layer overlying the first conductive layer;
forming a dual damascene via structure within the second interlayer dielectric layer;
depositing a barrier metal layer within the dual damascene via structure to form a liner that covers exposed regions of the dual damascene via structure;
electro-plating an aluminum layer onto the liner to fill the via structure with an aluminum material, the via structure being coupled to at least one transistor in the transistor layer through the first conductive layer; and
polishing the aluminum layer using a chemical mechanical planarization process to form at least a portion of a pixel element from a portion of the aluminum material.
2 . The method of claim 1 , wherein the second interlayer dielectric layer comprises a doped silicon glass.
3 . The method of claim 1 , wherein the portion of the pixel element is one of a plurality of pixel elements for the liquid crystal on silicon display device.
4 . The method of claim 1 , wherein the barrier metal layer comprises titanium nitride.
5 . The method of claim 1 , wherein the first interlayer dielectric layer comprises BPSG.
6 . The method of claim 1 , wherein a surface region of the aluminum layer is free from dishing or scratching from the chemical mechanical planarization process.
7 . The method of claim 1 , wherein the aluminum material is characterized by a reflectivity of 93% and greater.
8 . The method of claim 1 , wherein the portion of the pixel element is coupled to an MOS device.
9 . The method of claim 8 , wherein the MOS device is adapted to apply voltage to the portion of the pixel element and acts as an electrode.
10 . The method of claim 9 , wherein the portion of the pixel element is characterized by a size of about eight by eight microns in dimension.
11 . The method of claim 1 , wherein the pixel element comprises a thickness ranging from about 2000 Angstroms to about 4000 Angstroms.
12 . A liquid crystal on silicon (LCOS) device, the device comprising:
a semiconductor substrate;
an MOS device layer overlying the semiconductor substrate, the MOS device layer having a plurality of MOS devices;
a planarized interlayer dielectric layer overlying the MOS device layer;
a plurality of dual damascene via structures within the planarized interlayer dielectric layer, each of the dual damascene via structures comprising:
a via region within a first portion of the planarized interlayer dielectric layer, the via region having a first width and a first depth;
a surface region within a second portion of the planarized interlayer dielectric layer, the surface region having a second width, the surface region being coupled to the via region;
a plated aluminum metal layer to fill each of the dual damascene via structures including the via region and surface region for each of the dual damascene via structures to form respective plurality of electrode regions corresponding to each of the recessed regions, each of the electrode regions being respectively coupled to at least one of the MOS devices among the plurality of MOS devices.
13 . The device of claim 12 , wherein each of the electrode regions corresponds to a pixel element.
14 . The device of claim 12 , wherein the planarized interlayer dielectric layer comprising the first portion and the second portion.
15 . The device of claim 12 , wherein the planarized interlayer dielectric layer comprises BPSG.
16 . The device of claim 12 further comprising a liner layer on and in contact with exposed regions of the plurality of dual damascene via structures.
17 . The device of claim 12 further comprising a protective layer overlying the plated aluminum metal layer.
18 . The device of claim 17 further comprising a liquid crystal material overlying the protective layer.