Amplitude-stabilized odd order pre-distortion circuit

1. An amplitude-stabilized third-order predistortion circuit comprising:

a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage;

a plurality of replica cells having a differential input for receiving a differential level of input voltage, a differential output, and a load control input; and

a plurality of control circuits coupled to the differential outputs of the replica cells, and driving the load control inputs of the replica cells and the inputs of a signal combiner driving the main cell.

2. The circuit of claim 1 wherein the main cell comprises a variable load.

3. The circuit of claim 1 wherein the replica cells comprise a variable load.

4. The circuit of claim 1 wherein the main cell comprises a cross-coupled differential cell.

5. The circuit of claim 1 wherein the replica cells comprise a cross-coupled differential cell.

6. The circuit of claim 1 wherein the control circuit comprises a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the first single-ended peak signal and a single-ended peak reference signal.

7. The circuit of claim 1 wherein the plurality of the control circuits each comprise a differential amplifier.

8. The circuit of claim 1 wherein the control circuit comprises:

a first transistor having a control terminal, and coupled to a first current source at a first intermediate terminal;

a second transistor having a control terminal, and coupled to a second current source at a second intermediate terminal; and

a differential amplifier coupled to the first and second intermediate terminals for generating the load control voltage.

9. The circuit of claim 8 further comprising a sub-circuit interposed between the second transistor and the second current source to generate an adjustable voltage drop.

10. The circuit of claim 9 where the sub-circuit interposed between the second transistor and the second current source is a variable resistor device.

11. The circuit of claim 1 where the signal combiner comprises a summer.

12. An amplitude-stabilized third-order predistortion circuit comprising:

a first third-order predistortion circuit having an input for receiving an input signal, an output for providing a correction output signal, and a variable load;

a plurality of second third-order predistortion circuits having an input for receiving a peak input signal, an output for providing a correction peak output signal, and a variable load; and

a plurality of gain and loop stabilization circuits having a first input for receiving the correction peak output signal, a second input for receiving a correction amplitude set point, and an output driving the variable load control inputs of the second third-order predistortion circuits and the inputs of a signal combiner driving the variable load of the first third-order predistortion circuit,

wherein the second third-order predistortion circuits are replicas of the first third-order predistortion circuit.

13. The circuit of claim 12 wherein the variable load of the first and of the plurality of second third-order predistortion circuits comprises an active load.

14. The circuit of claim 12 wherein the first and the plurality of the second third-order predistortion circuits comprise a cross-coupled differential cell.

15. The circuit of claim 12 wherein the first and the plurality of the second third-order predistortion circuits comprise a cascade of multiplier cells.

16. The circuit of claim 12 wherein the plurality of the gain and loop stabilization circuits each comprise a differential amplifier.

17. The circuit of claim 12 where the signal combiner comprises a summer.

18. An amplitude-stabilized odd order predistortion circuit comprising:

a first odd-order predistortion circuit having an input for receiving an input signal, an output for providing a correction output signal, and a variable load;

a plurality of second odd-order predistortion circuits having an input for receiving a peak input signal, an output for providing a correction peak signal, and a variable load; and

a plurality of gain and loop stabilization circuits having a first input for receiving the correction peak output signal, a second input for receiving a correction amplitude set point, and an output driving the variable load control inputs of the second odd-order predistortion circuits and the inputs of a signal combiner driving the variable load of the first odd-order predistortion circuit,

wherein the second odd-order predistortion circuits are replicas of the first odd-order predistortion circuit.

19. The circuit of claim 18 wherein the variable load of the first and of the plurality of the second odd-order predistortion circuits comprises an active load.

20. The circuit of claim 18 wherein the first odd-order predistortion circuit and the plurality of the second odd-order predistortion circuits comprise a cascade of a plurality of cross-coupled differential cells.

21. The circuit of claim 18 wherein the first odd-order predistortion circuit and the plurality of second odd-order predistortion circuits comprise a cascade of a plurality of multiplier and cross-coupled differential cells.

22. The circuit of claim 18 wherein the first odd-order predistortion circuit and the plurality of second odd-order predistortion circuits comprise a plurality of multiplier and cross-coupled differential cells coupled according to a binary tree topology.

23. The circuit of claim 18 wherein the plurality of the gain and loop stabilization circuits each comprise a differential amplifier.

24. The circuit of claim 18 wherein the plurality of the gain and loop stabilization circuits each comprise a desired set-point for the correction amplitude level.