System and method of reading data using a reliability measure
View Patent ↗In a particular embodiment, a data storage device includes a memory array including a target memory cell and one or more other memory cells. The data storage device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array.
1. A method for reading data from a target memory cell, the method comprising:
in a data storage device including the target memory cell and one or more other memory cells, performing:
determining a value associated with a voltage of the target memory cell;
determining one or more corresponding values, wherein each of the one or more corresponding values is associated with a voltage of a respective one of the one or more other memory cells;
directly computing a reliability measure for at least one bit stored in the target memory cell based on the value associated with the voltage of the target memory cell and based on the one or more corresponding values; and
initiating a decode operation to decode data including the at least one bit using the reliability measure.
2. The method of claim 1 , wherein directly computing the reliability measure is performed by applying a parametric model to the value and to the one or more corresponding values.
3. The method of claim 2 , wherein the parametric model is generated by curve fitting a log likelihood ratio into a parametric function.
4. The method of claim 1 , wherein directly computing the reliability measure is performed by:
locating an entry in a table based on the value associated with the voltage of the target memory cell and based on the one or more corresponding values; and
reading the reliability measure from the located entry of the table.
5. The method of claim 4 , wherein data is provided to the table via a source external to the data storage device.
6. The method of claim 5 , wherein the data is provided based on one of:
calibrating the table during manufacture of the data storage device; and
a pre-computed table based on memory technology qualification data.
7. The method of claim 5 , wherein the data is provided based on a statistical analysis of a memory that includes the target memory cell and the one or more other memory cells.
8. The method of claim 4 , wherein the table is chosen based at least in part on one of:
a used reading resolution; and
a used reading threshold.
9. The method of claim 4 , wherein the table is chosen based at least in part on one of:
a number of neighboring cells that are used for producing a soft bit estimate;
one of a block number and a page number;
a cell error rate estimation; and
a number of error correction code parity checks.
10. The method of claim 4 , wherein the table is chosen based at least in part on one of:
a number of write cycles or a number of erase cycles of a read block or a read page;
a parameter that is associated with an elapsed time; and
a temperature of the data storage device during one or more of reading and programming a memory cell.
11. The method of claim 4 , wherein the table is chosen based at least in part on one of:
cell voltage distribution characteristics; and
results of previous decoding attempts associated with the target memory cell.
12. The method of claim 4 , wherein the table is populated with data based on a probability density function of target cell values.
13. The method of claim 12 , wherein the probability density function is estimated using a histogram of read target cell values.
14. The method of claim 1 , wherein the one or more other memory cells includes two memory cells and wherein the two memory cells are coupled to a same wordline as the target memory cell.
15. The method of claim 1 , wherein the one or more other memory cells includes one or more neighbor cells to the target memory cell, wherein the target memory cell is coupled to a first wordline and at least one neighbor cell is coupled to a second wordline.
16. A data storage device comprising:
a memory including a target memory cell and one or more other memory cells;
a controller coupled to the memory,
wherein the controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory; and
an error correction code (ECC) decoder coupled to the controller and configured to receive the reliability measure and to decode data including the at least one bit using the reliability measure.
17. The data storage device of claim 16 , wherein the controller is further configured to:
locate an entry in a table based on the voltage value associated with the target memory cell and based on the one or more corresponding voltage values; and
read the reliability measure from the located entry of the table.
18. The data storage device of claim 16 , wherein the controller is configured to directly compute the reliability measure by applying a parametric model to the voltage value and to the one or more corresponding voltage values.
19. The data storage device of claim 18 , wherein the parametric model is generated by curve fitting a log likelihood ratio into a parametric function.
20. The data storage device of claim 16 , wherein the one or more other memory cells include two memory cells and wherein the two memory cells are coupled to a same wordline as the target memory cell.
21. The data storage device of claim 16 , wherein the one or more memory cells include one or more neighbor cells to the target memory cell, wherein the target memory cell is coupled to a first wordline and at least one of the one or more neighbor cells is coupled to a second wordline.