Semiconductor structures including dual fins
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
1. A semiconductor structure, comprising:
a substrate with at least one protruding region between adjacent trenches formed therein;
a recess in the at least one protruding region of the substrate, the recess terminating above the adjacent trenches and having a bowl-shaped lower surface, protruding fin-like structures on opposite sides of the recess;
a semicircular opening in at least one sidewall of each of the fin-like structures, the bowl-shaped lower surface of the recess contacting the semicircular opening; and
a dielectric material filling the adjacent trenches.
2. The semiconductor structure of claim 1 , wherein the substrate comprises a silicon substrate.
3. The semiconductor structure of claim 1 , wherein the adjacent trenches have sloped or angled sidewalls.
4. The semiconductor structure of claim 1 , wherein the adjacent trenches extend further into the substrate than the recess.
5. The semiconductor structure of claim 1 , further comprising a mask disposed over planar upper surfaces of the fin-like structures.
6. The semiconductor structure of claim 1 , further comprising another dielectric material filling the semicircular opening.
7. The semiconductor structure of claim 1 , wherein each of the fin-like structures is spaced apart from an underlying region of the substrate by the semicircular opening.
8. The semiconductor structure of claim 1 , wherein the dielectric material comprises silicon dioxide.
9. The semiconductor structure of claim 1 , wherein the dielectric material has an upper surface substantially coplanar with a lower surface of the recess.
10. The semiconductor structure of claim 1 , wherein the dielectric material has an upper surface below a lower surface of the recess.
11. The semiconductor structure of claim 1 , further comprising doped regions in unrecessed portions of the at least one protruding region on laterally opposite ends of the recess.
12. The semiconductor structure of claim 1 , further comprising a conductive gate material extending over a portion of the dielectric material and sidewalls of the adjacent trenches, the conductive gate material terminating on ends of the fin-like structures.
13. A semiconductor structure, comprising:
a plurality of trenches formed in a substrate and at least partially filled with a dielectric material;
an array of recesses with fin-like structures protruding on opposite sides formed in regions of the substrate between the plurality of trenches, the fin-like structures having sloped sidewalls; and
a mask material disposed over and terminating on surfaces at ends of the fin-like structures, sidewalls of the mask material substantially contiguous with the sloped sidewalls of the fin-like structures.
14. The semiconductor structure of claim 13 , wherein an upper surface of the dielectric material is substantially coplanar with a lower surface of the array of recesses.
15. The semiconductor structure of claim 13 , wherein the surfaces at the ends of the fin-like structures are substantially planar.
16. A semiconductor structure, comprising:
at least one pair of trenches in a substrate;
a dielectric material at least partially filling the at least one pair of trenches;
a recessed region between the at least one pair of trenches, the recessed region having a depth less than a depth of the at least one pair of trenches, sidewalls of the recessed region and the at least one pair of trenches defining fin structures therebetween;
an oxide material overlying a portion of the dielectric material, extending onto sidewalls of the at least one pair of trenches, and terminating on upper surfaces of the fin structures; and
an electrode overlying the oxide material.
17. The semiconductor structure of claim 16 , wherein the upper surfaces of the fin structures are substantially planar.