Method for forming gate oxide of semiconductor device
View Patent ↗Disclosed herein is a method for forming a triple gate oxide of a semiconductor device. The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region where a gate oxide having a first thickness will be formed, a second region where a gate oxide having a second thickness will be formed and a third region where a gate oxide having a third thickness will be formed on a semiconductor substrate, forming a first oxide film through wet oxidation on the semiconductor substrate and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, which are formed on the second region and the third region, forming a third oxide film through thermal oxidation on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film, which is formed on the third region, and forming a fourth oxide film through thermal oxidation on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure of the first oxide film/second oxide film/nitride film is formed in the first region, a gate oxide having a double structure of the third oxide film/nitride film is formed in the second region and a gate oxide having a double structure of the fourth oxide film/nitrate film is formed in the third region.
1. A gate oxide of a semiconductor device comprising:
a semiconductor substrate divided into a first region, a second region, and a third region;
a first gate oxide layer formed in a triple structure of a first silicon oxide film/second silicon oxide film/nitride film on the first region;
a second gate oxide layer formed in a double structure of a third oxide film/nitride film on the second region; and
a third gate oxide layer formed in a double structure of a fourth oxide film/nitride film on the third region.
2. The gate oxide of a semiconductor device of claim 1 , wherein the thickness ratio of the first silicon oxide film to the second silicon oxide film is 1:20.
3. The gate oxide of a semiconductor device of claim 2 , wherein the first silicon oxide film is formed by a thickness in the range of 40 to 220Å and the second silicon oxide film is formed by a thickness in the range of 200 to 1100Å.
4. The gate oxide of a semiconductor device of claim 1 , wherein the first silicon oxide film is formed in the ambient of H 2 /O 2 at a temperature in the range of 800 to 900° C. through wet oxidation.
5. The gate oxide of a semiconductor device of claim 1 , wherein the second silicon oxide film corresponds to a TEOS oxide formed through LP-CVD.
6. The gate oxide of a semiconductor device of claim 1 , wherein the second silicon oxide film is formed at a low temperature in the range of 600 to 650° C.
7. The gate oxide of a semiconductor device of claim 1 , wherein the third oxide film is formed by a thickness in the range of 100 to 150Å.
8. The gate oxide of a semiconductor device of claim 1 , wherein the third oxide film is formed in the ambient of H 2 /O 2 at a high temperature in the range of 800 to 900° C. such that the second silicon oxide film is heat-treated to be hardened while the third oxide film is formed.
9. The gate oxide of a semiconductor device of claim 1 , wherein the fourth oxide film is formed by a thickness in the range of 15 to 20Å on the third region in the ambient of H 2 /O 2 at a temperature in the range of 650 to 700° C.
10. The gate oxide of a semiconductor device of claim 1 , wherein the nitride film is formed through plasma nitridation.
11. The gate oxide of a semiconductor device of claim 10 , wherein the plasma nitridation is performed at a temperature in the range of 400 to 450° C. using remote plasma.
12. The gate oxide semiconductor device of claim 1 , wherein the first gate oxide layer is spaced apart from the second gate oxide layer.
13. The gate oxide semiconductor device of claim 1 , wherein the second gate oxide layer is spaced apart from the third gate oxide layer.
14. The gate oxide semiconductor device of claim 1 , wherein the semiconductor substrate comprises a first isolation layer disposed between the first region and the second region, and a second isolation layer disposed between the second region and the third region.