Structure and method for biasing phase change memory array for reliable writing
A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
1. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure within the integrated circuit for writing to the memory cells comprising:
a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;
a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and
a bit line driver receiving the controlled current and an unselected bit line voltage, the bit line driver selecting between providing to a bit line the controlled current and the unselected bit line voltage in response to a driver control signal, the bit line providing the controlled current to at least one of the memory cells comprising phase change memory elements.
2. The structure of claim 1 , wherein the driver control signal is an output signal from a decoder.
3. The structure of claim 1 , further including a deselection control device which causes the bit line driver to apply the unselected bit line voltage when the pulse width control transistor is off.
4. The structure of claim 3 , wherein when the pulse width control transistor is off, the deselection control device connects the unselected bit line voltage to a terminal for providing the controlled current to the bit line driver.
5. The structure of claim 1 , further including a second bit line driver receiving a second controlled current from a second slave arm of a second current minor as controlled by a second pulse width control transistor in series with the second slave arm, the second bit line driver being controlled by the driver control signal.
6. The structure of claim 5 , wherein the second bit line driver provides the second controlled current to a second bit line as the bit line driver provides the unselected bit line voltage to the bit line.
7. The structure of claim 5 , wherein the second bit line driver provides the second controlled current to a second bit line as the bit line driver provides the controlled current to the bit line.
8. The structure of claim 7 , wherein the second controlled current is substantially different from the controlled current.
9. The structure of claim 5 , wherein the bit line and the second bit line are in different memory cell layers.
10. The structure of claim 1 , further comprising a pulse width controller for controlling the pulse width.
11. The structure of claim 10 , wherein the pulse width controller causes the pulse width to be about 200 nanoseconds for resetting a memory cell and between 500 and 1000 nanoseconds for setting a memory cell.
12. The structure of claim 1 , wherein the control current causes the controlled current to be about 20 microamps for setting a memory cell, and about 100 microamps for resetting a memory cell.
13. The structure of claim 1 , wherein each of the memory cells comprising phase change memory elements comprises a diode in series with a phase change memory element.
14. The structure of claim 1 , wherein the memory cells are formed in a plurality of layers above a substrate.
15. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure for fast successive writing to the memory cells comprising:
a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;
a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width;
a deselection control device for providing an unselected voltage to the output terminal at times not within the pulse width; and
structure for connecting the output terminal to terminals of a plurality of the memory cells.
16. The structure of claim 15 , wherein the structure for connecting the output terminal to terminals of a plurality of the memory cells comprises a plurality of drivers, the plurality of drivers each connecting the output terminal to a bit line in response to a different bit line decoder output signal.
17. The structure of claim 15 , wherein the structure for connecting the output terminal to terminals of a plurality of the memory cells comprises a plurality of drivers, the plurality of drivers each connecting the output terminal to a word line in response to a different word line decoder output signal.
18. The structure of claim 15 , wherein the plurality of memory cells are formed in a plurality of memory cell layers above a substrate.
19. The structure of claim 15 , wherein the memory cells comprising phase change memory elements each comprise a phase change memory element in series with a diode.
20. An integrated circuit structure comprising:
a structure for writing to memory cells comprising phase change memory elements, the structure for writing comprising:
a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;
a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and
a plurality of memory cells for storing integrated circuit control information, each comprising a series combination of: a phase change material and an antifuse.
21. The integrated circuit structure of claim 20 , wherein the pulse width control transistor in series with the current minor is in series with the slave arm of the current minor.
22. The integrated circuit structure of claim 20 , wherein the memory cells are formed in a plurality of memory cell layers above a substrate.
23. The integrated circuit structure of claim 20 , wherein the series combination of a phase change material and an antifuse comprises a series combination of a phase change material, an antifuse, and a diode.
24. An integrated circuit memory comprising:
a plurality of memory cells layers, each memory cell layer comprising:
a layer of bit lines extending in a first direction;
a layer of word lines extending in a second direction; and
a layer of phase change memory cells, each phase change memory cell extending between one of the bit lines and one of the word lines; and
structure for controlling current and pulse width for writing the phase change memory cells comprising:
a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; and
a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width.
25. The integrated circuit memory of claim 24 , wherein the output terminal supplies a bit line bias applied by a bit line decoder to a bit line of a memory array.
26. The integrated circuit memory of claim 24 , wherein the output terminal supplies a word line bias applied by a word line decoder to a word line of a memory array.
27. The integrated circuit memory of claim 24 , wherein the controlled current and the pulse width are selected to cause a memory cell to move to a selected state.
28. The integrated circuit memory of claim 27 , wherein the selected state is an amorphous state representing a reset state or a logic 0.
29. The integrated circuit memory of claim 27 , wherein the selected state is a crystalline state representing a set state or a logic 1.
30. The integrated circuit memory of claim 24 , wherein each of the phase change memory cells also comprises a diode.