IP Library Granted Patent US 8,634,173
Granted Patent B2
US 8,634,173 · App. 12/958,256 · Granted Jan 21, 2014

Semiconductor apparatus

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,634,173
App. No.
12/958,256
Granted
Jan 21, 2014
Kind
B2
Abstract

A semiconductor apparatus includes: first and second power-supply terminals; an internal circuit connected between the first and second power-supply terminals; and a protection circuit connected in parallel with the internal circuit between the first and second power-supply terminals, the protection circuit including: a series circuit that includes a resistor and a first capacitor, and is connected in parallel with the internal circuit between the first and second power-supply terminals; a first MOS transistor that is connected in parallel with the series circuit, and is controlled according to a voltage at a connection point between the resistor and the first capacitor; and a switch circuit that is connected in parallel with the resistor, is turned on in a delayed manner after a power-supply voltage is applied between the first and second power-supply terminals, and changes the voltage at the connection point so that the first MOS transistor is turned off.

Claims (37)

1. A semiconductor apparatus comprising:

a first power supply terminal and a second power supply terminal;

an internal circuit connected between the first power supply terminal and the second power supply terminal; and

a protection circuit connected in parallel with the internal circuit between the first power supply terminal and the second power supply terminal,

the protection circuit including:

a series circuit including a resistor and a first capacitor connected in series, the series circuit connected in parallel with the internal circuit between the first power supply terminal and the second power supply terminal;

a first MOS transistor connected in parallel with the series circuit, the first MOS transistor configured to be controlled in accordance with a voltage at a connection point between the resistor and the first capacitor; and

a switch circuit connected in parallel with the resistor, the switch circuit configured to be turned on in a delayed manner after a power supply voltage is applied between the first power supply terminal and the second power supply terminal and to change the voltage at the connection point so that the first MOS transistor is turned off.

2. The semiconductor apparatus of claim 1 , wherein

the switch circuit includes:

a second MOS transistor connected in parallel with the resistor; and

a voltage supply circuit configured to supply a predetermined voltage for turning on the second MOS transistor to a gate of the second MOS transistor, after the power supply voltage is applied between the first power supply terminal and the second power supply terminal.

3. The semiconductor apparatus of claim 2 , wherein

the voltage supply circuit includes:

a current source configured to supply a predetermined current after the power supply voltage is applied between the first power supply terminal and the second power supply terminal; and

a second capacitor configured to be charged or discharged by the predetermined current and generate the predetermined voltage.

4. The semiconductor apparatus of claim 1 further comprising:

an input/output terminal; and

first and second diodes connected between the input/output terminal and the first power supply terminal and between the input/output terminal and the second power supply terminal, respectively, the first and second diodes applied with a reverse bias voltage by the power supply voltage.

5. The semiconductor apparatus of claim 2 further comprising:

an input/output terminal; and

first and second diodes connected between the input/output terminal and the first power supply terminal and between the input/output terminal and the second power supply terminal, respectively, the first and second diodes applied with a reverse bias voltage by the power supply voltage.

6. The semiconductor apparatus of claim 3 further comprising:

an input/output terminal; and

first and second diodes connected between the input/output terminal and the first power supply terminal and between the input/output terminal and the second power supply terminal, respectively, the first and second diodes applied with a reverse bias voltage by the power supply voltage.

7. The semiconductor apparatus of claim 1 further comprising

at least one inverter connected between the connection point and the gate of the first MOS transistor.

8. The semiconductor apparatus of claim 2 further comprising

at least one inverter connected between the connection point and the gate of the first MOS transistor.

9. The semiconductor apparatus of claim 3 further comprising

at least one inverter connected between the connection point and the gate of the first MOS transistor.

10. The semiconductor apparatus of claim 4 further comprising

at least one inverter connected between the connection point and the gate of the first MOS transistor.

11. The semiconductor apparatus of claim 5 further comprising

at least one inverter connected between the connection point and the gate of the first MOS transistor.

12. The semiconductor apparatus of claim 6 further comprising

at least one inverter connected between the connection point and the gate of the first MOS transistor.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032022/0269 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2011
From: AKAI, KAZUMASA; NAKAHATA, MASAHIRO
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 025738/0385 →