Loaded printed circuit board test fixture and method for manufacturing the same
View Patent ↗A test fixture for testing loaded printed circuit boards having a plurality of test points having a probe plate including an array of widely spaced high force spring test probes in compliant contact with solid translator pins located in a translator fixture removably positioned over the probe plate. The test fixture includes optimization software wherein translation of the test signals are optimized by providing the shortest interconnect distance in the x-y plane between the test points on the printed circuit board and the test probes in the probe plate. The fixture further includes an unpowered opens device for testing components on the loaded printed circuit board.
1. A loaded board test fixture for testing a plurality of closely spaced test points on a loaded printed circuit board comprising:
an array of relatively widely spaced apart high spring force test probes extending through a probe plate and adapted for electrically connecting to an external electronic test analyzer;
a translator fixture removably positioned over the high spring force test probes and adjacent the closely spaced test points on the circuit board;
the translator fixture having a top plate for receipt of circuit board components so that an upper surface of the top plate is substantially adjacent to the test points on a loaded printed circuit board and a plurality of parallel plates below the top plate;
a plurality of translator pins supported in the translator fixture for alignment with the test probes at one end of the translator fixture and with the closely spaced test points at the opposite end of the translator fixture, the translator pins comprising solid pins having sufficient axial rigidity to effectively translate test forces applied by the test probes to the closely spaced test points, and wherein the test probes are in compliant contact with the translator pins for translating said test forces and electrical test signals between the closely spaced test points on the printed circuit board and connections to the external electronic test analyzer; and
optimization means that determines the placement of the translator pins in the translator fixture by determining final hole drilling locations in the top plate and plurality of parallel plates based upon the shortest interconnect distance between the closely spaced test points and the test probes for the translator pins.
2. The test fixture of claim 1 wherein the optimization means is computer software.
3. The test fixture of claim 1 further comprising an unpowered opens device positioned within the translator fixture for electrically translating test signals from loaded circuit board components to the test probes.
4. The test fixture of claim 1 further including a multiplex adapter within the test fixture between the translator pins and the test probes.
5. The test fixture of claim 1 wherein the translator fixture further includes at least one force applying blind pin.
6. The test fixture of claim 1 wherein the translator fixture further includes a plurality of spaced apart translator plates wherein the translator pins extend through holes in the translator plates.
7. The test fixture of claim 6 wherein at least one translator plate has a recess in a top surface and recess in a bottom surface creating a web having a hole for guiding a translator pin.
8. The test fixture of claim 3 wherein the unpowered opens device has a set block fastened to a bottom translator plate in the translator fixture.
9. The test fixture of claim 5 wherein the translator fixture has at least two translator pins wired together.
10. A method for determining an optimized translation of translator pins within a translator fixture between test locations on a loaded printed circuit board under test and tester interface locations comprising the steps of:
determining drilling and pocket milling requirements for properly positioning the loaded printed circuit board under test on the translator fixture;
the drilling requirements including determining final hole drilling locations through multiple parallel plates in the translator fixture based upon the shortest interconnect distance between the test locations and the tester interface locations;
performing a pin mapping algorithm to assigned test point locations for the loaded printed circuit board under test to the tester interface locations by angling translator pins in such a way as to minimize lateral and directional forces; and
performing a pin sizing algorithm to automatically determine optimal translator pin diameter and length.
11. The method of claim 10 wherein the pin mapping algorithm determines interface properties including analog signal, digital signal, power supply, ground, peripheral, ASRU, resistor termination, test jet or polarity check.
12. The method of claim 10 wherein the pin sizing algorithm determines the optimal translator pin diameter and length based upon application, pin angle and test locations characteristics.