Method for manufacturing twin bit structure cell with silicon nitride layer
A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure.
1. A method for forming a twin bit cell structure for a flash memory device, the method comprising:
providing a semiconductor substrate including a surface region;
forming a gate dielectric layer overlying the surface region;
forming a polysilicon gate structure overlying the gate dielectric layer;
forming first and second undercut regions underneath the polysilicon gate structure in first and second portions of the gate dielectric layer;
exposing the semiconductor substrate, the gate dielectric layer, the undercut regions, and the polysilicon gate structure to an oxidizing environment to cause:
formation of a first silicon oxide layer overlying a top surface, side surfaces, and bottom surfaces facing the undercut regions of the polysilicon gate structure, and
formation of a second silicon oxide layer overlying a portion of the surface region of the semiconductor substrate;
depositing a silicon nitride material over the first and second silicon oxide layers and filling the undercut regions;
selectively etching a first portion of the silicon nitride material overlapped by the polysilicon gate structure;
maintaining a second portion the silicon nitride material in an insert region in a portion of each of the undercut regions; and
forming a sidewall spacer structure, wherein the sidewall spacer structure is formed so as to overlie each of the side surfaces of the polysilicon gate structure, to overlie exposed surfaces of the silicon nitride material, and to overlie an exposed surface portion of the second oxide layer,
wherein the sidewall spacer structure contacts the exposed surfaces of the silicon nitride material at a contact interface, and wherein the contact interface is overlapped by the polysilicon gate structure in the undercut regions underneath the polysilicon gate structure.
2. The method of claim 1 further comprising forming a source region and a drain region.
3. The method of claim 1 wherein the sidewall spacer structure is formed by depositing a conformal dielectric layer overlying the polysilicon gate structure followed by a selective etching process.
4. The method of claim 1 wherein the semiconductor substrate is a P-type silicon wafer.
5. The method of claim 1 wherein the undercut region is formed using a self-limiting etching process.
6. The method of claim 1 wherein the undercut region is a void region.
7. The method of claim 1 wherein the silicon nitride material is characterized by a dielectric k value of about eight and greater.
8. The method of claim 1 wherein the silicon nitride material is formed using atomic layer deposition.
9. The method of claim 8 wherein the silicon nitride material has a silicon to nitrogen ratio of about 1:1.1 to about 1:1.3.
10. The method of claim 1 wherein the silicon nitride material in each of the undercut regions provides a charge storage for the twin bit cell structure.
11. The method of claim 1 wherein the silicon nitride material is characterized by a first thickness, the first thickness being controlled by a thickness of the gate dielectric layer.
12. The method of claim 1 further comprises forming active regions in a vicinity of the surface region of the semiconductor substrate.
13. The method of claim 12 wherein the active regions are formed by an implantation process using an N type arsenic as an impurity species and the polysilicon gate structure, including the sidewall spacer structure as a mask.
14. The method of claim 1 wherein the selective etching process comprises a reactive ion etching process.