Local interconnect having increased misalignment tolerance
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.
1. A semiconductor device comprising:
a substrate having a source region;
a pair of source select transistors formed above the substrate on opposite sides of the source region;
an inter-layer dielectric formed above the substrate between the pair of source select transistors; and
a local interconnect, comprising a metal, formed to adjacent the inter-layer dielectric,
a width of the local interconnect being less than a distance between the pair of source select transistors, and
a source select transistor, of the pair of source select transistors, including:
a first dielectric layer formed on the substrate,
a charge storage layer formed on the first dielectric layer,
a second dielectric layer formed on the charge storage layer, and
a control gate layer formed on the second dielectric layer.
2. The semiconductor device of claim 1 , where each side of the local interconnect is separated from a dielectric, formed adjacent a sidewall of a respective one of the pair of source select transistors, by between 20 nm and 30 nm.
3. The semiconductor device of claim 1 ,
where the source region includes a source silicide region formed on at least a portion of an upper surface of the source region, and
where the width of the local interconnect is at least as wide as the source silicide region.
4. The semiconductor device of claim 1 ,
where the control gate layer includes a polysilicon layer, and
where a thickness of the polysilicon layer ranges from about 1000 Å to about 2000 Å.
5. The semiconductor device of claim 1 ,
where the charge storage layer comprises a silicon nitride layer, and
where a thickness of the silicon nitride layer ranges from about 25 Å to about 500 Å.
6. The semiconductor device of claim 1 , where the width of the local interconnect area is between 40 nm and 60 nm less than the distance between the pair of source select transistors.
7. The semiconductor device of claim 1 , further comprising a mask layer formed over the pair of select transistors and the inter-layer dielectric.
8. A device comprising:
a pair of select transistors formed on a substrate of the device;
an inter-layer dielectric deposited between sidewall spacers of the pair of select transistors,
a silicide region being formed on an upper surface of a source region that is formed between the pair of select transistors;
an interconnect area formed based on the inter-layer dielectric,
a width of the interconnect area being less than a distance between the pair of select transistors; and
a mask layer formed over the pair of select transistors and the inter-layer dielectric,
the mask layer defining the interconnect area between the pair of select transistors, and
the inter-layer dielectric being etched to form the interconnect area.
9. The device of claim 8 , further comprising:
a contact formed within the interconnect area.
10. The device of claim 8 , further comprising:
a barrier layer formed over the interconnect area.
11. The device of claim 10 , where the barrier layer includes at least one of:
a titanium layer, a thickness of the titanium layer ranging from about 50 Å to about 300 Å, or
a titanium nitride layer, a thickness of the titanium nitride layer ranging from about 50 Å to about 300 Å.
12. The device of claim 8 , where one of the pair of select transistors includes:
a first dielectric layer formed over the substrate,
a charge storage layer formed over the first dielectric layer, and
a control gate layer formed over the charge storage layer.
13. The device of claim 12 ,
where the charge storage layer comprises a silicon nitride layer, and
where a thickness of the silicon nitride layer ranges from about 25 Å to about 500 Å.
14. The device of claim 12 ,
where the control gate layer includes a polysilicon layer, and
where a thickness of the polysilicon layer ranges from about 1000 Å to about 2000 Å.
15. The device of claim 8 , where each side of the interconnect area is separated from a dielectric, formed adjacent a sidewall of a respective one of the pair of source select transistors, by between 20 nm and 30 nm.
16. A device comprising:
a pair of select transistors formed on a substrate on opposite sides of a source region of the substrate;
an inter-layer dielectric deposited between sidewall spacers of the pair of select transistors; and
an interconnect area formed based on the inter-layer dielectric,
where a distance between the pair of select transistors being greater than a width of the interconnect area and
a barrier layer formed over the interconnect area,
the barrier layer including at least one of:
a titanium layer, a thickness of the titanium layer ranging from about 50 Å to about 300 Å, or
a titanium nitride layer, a thickness of the titanium nitride layer ranging from about 50 Å to about 300 Å.
17. The device of claim 16 , further comprising:
a liner oxide layer formed over the pair of select transistors and the source region, the sidewall spacers being formed over the line oxide layer.
18. The device of claim 16 , further comprising:
a silicide region formed on an upper surface of the source region,
the silicide region including at least one of tungsten, cobalt, titanium, tantalum nickel, or molybdenum, and
a thickness of the silicide region ranging from about 50 Å to about 500 Å.
19. The device of claim 16 , where the width of the interconnect area is between 40 nm and 60 nm less than the distance between the pair of select transistors.
20. The device of claim 16 , further comprising:
a contact formed within the interconnect area.