Nonvolatile semiconductor memory device and method of manufacturing the same
View Patent ↗The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.
1. A nonvolatile semiconductor memory device comprising:
a semiconductor layer of a first general conductive type;
a first element isolation layer and a second element isolation layer that are formed adjacent to each other in the semiconductor layer so as to elongate in a first direction in plan view of the memory device;
a trench disposed between the first and second isolation layers and comprising a first sidewall and a second sidewall opposite from the first sidewall, in the plan view of the memory device the first sidewall being parallel to a second direction that is perpendicular to the first direction and the second sidewall slanting from the second direction;
a source layer of a second general conductive type formed in the second sidewall of the trench and a bottom portion of the trench;
a first insulation film disposed on the first and the second sidewalls of the trench and on the bottom portion of the trench;
a floating gate disposed on the first insulation film in the trench;
a control gate disposed on the semiconductor layer so as to overlap the first and second element isolation layers partially in the plan view of the memory device, the control gate overlapping the floating gate partially; and
a second insulation film disposed between the control gate and the floating gate.
2. The nonvolatile semiconductor memory device of claim 1 , wherein the control gate overlaps the floating gate in the plan view of the memory device.
3. The nonvolatile semiconductor memory device of claim 1 , wherein the control gate overlaps the floating gate in a sectional view of the memory device.
4. The nonvolatile semiconductor memory device of claim 1 , wherein part of the floating gate is disposed in the trench.
5. The nonvolatile semiconductor memory device of claim 1 , wherein an end surface of the control gate and the first sidewall of the trench are flush with each other.
6. The nonvolatile semiconductor memory device of claim 1 , wherein the semiconductor layer comprises single crystal silicon and a plane orientation of the first sidewall is (100).
7. The nonvolatile semiconductor memory device of claim 1 , wherein the first insulation film formed on the second sidewall and the bottom of the trench is thicker than the first insulation film formed on the first sidewall.
8. The nonvolatile semiconductor memory device of claim 1 , wherein the trench comprises third and fourth sidewalls that are parallel to the first direction, and the first, second, third and fourth sidewalls form a trapezoid in the plan view of the trench.
9. A nonvolatile semiconductor memory device comprising:
a semiconductor layer of a first general conductive type;
a first element isolation layer and a second element isolation layer that are formed adjacent to each other in the semiconductor layer;
a trench disposed between the first and second isolation layers, the trench comprising two sidewalls each extending from the first element isolation layer to the second element isolation layer in plan view of the memory device, and one of the two sidewalls slanting from the other of the two sidewalls in the plan view of the memory device;
a source layer of a second general conductive type formed in the trench;
an insulation film disposed in the trench to cover the source layer;
a floating gate disposed on the insulation film in the trench; and
a control gate disposed on the semiconductor layer so as to overlap the floating gate partially.