IP Library Granted Patent US 8,421,185
Granted Patent B2
US 8,421,185 · App. 12/978,552 · Granted Apr 16, 2013

Parasitic vertical PNP bipolar transistor in BiCMOS process

Inventors: Tzuyin Chiu (Shanghai, CN); TungYuan Chu (Shanghai, CN); Wensheng Qian (Shanghai, CN); YungChieh Fan (Shanghai, CN); Donghua Liu (Shanghai, CN); Jun Hu (Shanghai, CN)
Assignee: Shanghai Hua Hong NEC Electronics Company, Limited
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Quick Facts
Patent No.
US 8,421,185
App. No.
12/978,552
Granted
Apr 16, 2013
Kind
B2
Abstract

A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.

Claims (8)

1. A parasitic vertical PNP device in a BiCMOS process with shallow trench isolation (STI) on bulk silicon substrate comprises:

a collector being formed by implanting p-type impurity in an active area;

pseudo buried layers at the bottom of the STI at both sides of the active area by implanting heavy dose of the p-type impurity into the bulk silicon substrate, wherein the pseudo buried layers is directly connected with the bulk silicon substrate, and forms a PN junction;

deep contacts wherein the deep contracts are through field oxide to connect to the pseudo buried layers and to pick up the collector;

a base being formed by ion implanting a n-type impurity layer wherein the base sits on top of the collector;

an emitter which is a single crystal p-type epitaxy layer wherein the emitter lies above the base and is connected directly by a metal contact; and

a portion of the p-type epitaxy layer on top of the base is converted into n-type and serves as a connection path of the base.

2. The parasitic vertical PNP device in a BiCMOS process as recited in claim 1 comprises, p type pseudo buried layer of connecting the collector with the ion implant dosage range 1e14˜1e16 cm −2 and energy below 45 keV.

Assignments (2)
MERGER Recorded May 13, 2014
From: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
To: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 032885/0047 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 25, 2010
From: CHIU, TZUYIN; CHU, TUNGYUAN; QIAN, WENSHENG; FAN, YUNGCHIEH; LIU, DONGHUA; HU, JUN
To: SHANGHAI HUA HONG NEC ELECTRONICS COMPANY, LIMITED
Reel/Frame 025568/0463 →
Priority Claims (1)
CN 2009 1 0202067 · Dec 31, 2009 · national
Continuity (1)
Related Publication 20110156202A1 · Jun 30, 2011