Semiconductor chip to dissipate heat, semiconductor package including the same, and stack package using the same

1. A semiconductor chip comprising:

a semiconductor chip body having a top surface, a bottom surface and side surfaces connecting the top surface and the bottom surface wherein a bottom surface of the semiconductor chip body possesses a groove pattern extending from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body;

through electrodes extending from a top surface of the semiconductor chip body and passing through the groove pattern defined on the bottom surface; and

a heat dissipation pattern filling in the groove pattern contacting the through electrodes.

2. The semiconductor chip according to claim 1 , wherein a width of the groove pattern corresponds to a diameter of the through electrodes.

3. The semiconductor chip according to claim 1 , wherein a width of the groove pattern is greater than a diameter of the through electrodes.

4. The semiconductor chip according to claim 1 , further comprising:

a heat dissipation member formed on at least two of the side surfaces of the semiconductor chip body and connected the with heat dissipation pattern.

5. The semiconductor chip according to claim 4 , wherein the heat dissipation members are separated from one another.

6. The semiconductor chip according to claim 4 , wherein the heat dissipation members cover the side surfaces in such a way as to be integrated with one another and surround the side surfaces of the semiconductor chip body.

7. The semiconductor chip according to claim 1 , wherein the heat dissipation pattern is formed of a heat transfer material layer.

8. The semiconductor chip according to claim 1 , wherein the groove pattern has a line portion extending from one or more side surfaces of the semiconductor chip body outlining the groove pattern, and the heat dissipation pattern has an enlarged portion extending from the line portion and surrounding the through electrodes.

9. The semiconductor chip according to claim 8 , further comprising:

an insulation layer pattern interposed between the heat dissipation pattern and the bottom surface of the semiconductor chip body including the groove pattern.

10. The semiconductor chip according to claim 8 , wherein the heat dissipation pattern has a first heat dissipation pattern formed in the line portion of the groove pattern and second heat dissipation patterns formed in the enlarged portions of the groove pattern.

11. The semiconductor chip according to claim 10 , wherein the first heat dissipation pattern is formed of a heat transfer material layer and the second heat dissipation patterns are formed of one of copper, aluminum and gold.

12. The semiconductor chip according to claim 9 , further comprising:

an additional insulation layer pattern formed on the bottom surface of the semiconductor chip body including the insulation layer pattern in such a way as to cover the bottom surface of the semiconductor chip body while having slits exposing the heat dissipation pattern and the through electrodes.

13. The semiconductor chip according to claim 12 , further comprising:

an additional heat dissipation pattern filled in the slit of the additional insulation layer pattern and connected with the heat dissipation pattern.

14. The semiconductor chip according to claim 13 , wherein the additional heat dissipation pattern is formed of a heat transfer material layer.

15. A semiconductor package comprising:

a semiconductor chip including a semiconductor chip body having a top surface and a bottoms surface that has a groove pattern extending from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body, through electrodes extending from a top surface of the semiconductor chip body and passing through the groove pattern defined on the bottom surface, and a heat dissipation pattern filling in the groove pattern on the bottom surface and contacting the through electrodes; and

a substrate on which the semiconductor chip is mounted, the substrate having connection pads connected with the through electrodes.

16. The semiconductor package according to claim 15 , further comprising:

an encapsulant formed to seal an upper surface of the substrate including the semiconductor chip; and

external connection terminals attached to a lower surface of the substrate.

17. A stack package comprising:

at least two vertically stacked semiconductor chips;

each semiconductor chip including

a semiconductor chip body having a top surface, a bottom surface with a groove pattern extending from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body, and side surfaces connecting the top surface and the bottom surface,

through electrodes extending from a top surface of the semiconductor chip body and passing through the groove pattern defined on the bottom surface, and

a heat dissipation pattern filling the groove pattern on the bottom surface and contacting the through electrodes,

wherein the stacked semiconductor chips are disposed such that their through electrodes contact each other to be electrically connected with each other.

18. The stack package according to claim 17 , wherein each of the stacked semiconductor chips further includes heat dissipation members formed on one or more side surfaces of the semiconductor chip body to be connected with the heat dissipation pattern.

19. The stack package according to claim 17 , further comprising:

a heat transfer adhesive covering the top surface of an uppermost semiconductor chip among the stacked semiconductor chips.

20. The stack package according to claim 19 , further comprising:

an additional heat dissipation member disposed on the additional heat transfer adhesive and connected with the heat dissipation members.