Manufacturing approach for collector and a buried layer of bipolar transistor
View Patent ↗This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.
1. A manufacturing process for a collector and a buried layer of a bipolar transistor, comprises:
step 1, depositing an ONO (oxide nitride oxide) hard mask on a silicon substrate surface; etching shallow trenches on the silicon substrate, wherein the depth of the shallow trenches is less than 2 μm; wherein the ONO hard mask includes a silicon oxide (SiO 2 ) layer in the bottom, silicon nitride (Si 3 N 4 ) in the middle and silicon oxide on the top;
step 2, depositing a silicon oxide film on the ONO hard mask; etching back the oxide film thus forming a silicon oxide spacer is on sidewalls of the shallow trenches;
step 3, doping the bottoms of shallow trenches with an impurity by ion implantation to form doped regions in the substrate near the bottom of the shallow trenches;
step 4, stripping the silicon oxide film by wet etch;
step 5, filling dielectric into the shallow trenches thus forming shallow trench isolations (STIs);
step 6, annealing the silicon substrate with a temperature anneal process to link the doped regions between the STIs through lateral diffusion thus forming a pseudo buried layer;
step 7, implanting the active region between the STIs and above the pseudo buried layer with one or more ion implantations; thus converting it into the collector.
2. The manufacturing process of claim 1 wherein a thickness of the bottom SiO 2 is between 100 and 300 Å, a thickness of the Si 3 N 4 layer is between 200 and 500 Å, and a thickness of the top SiO 2 is between 300 and 800 Å.
3. The manufacturing process of claim 1 wherein in step 2, a width of the oxide spacer formed on the sidewall of STI is about 300-1000 Å.
4. The manufacturing process of claim 1 wherein either a NPN bipolar transistor or a PNP bipolar transistor is formed;
wherein, if the NPN bipolar transistor is formed:
in step 1, the silicon substrate is p-type;
in step 3, the impurity is n-type and the doped regions are n-type;
in step 6, the pseudo buried layer is n-type and is doped;
in step 7, the one or more ion implantations are n-type and the collector is n-type;
wherein, if the PNP bipolar transistor is formed;
in step 1, the silicon substrate is n-type;
in step 3, the impurity is p-type and the doped regions are p-type;
in step 6, the pseudo buried layer is p-type and is doped;
in step 7, the one or more ion implantations are p-type and the collector is p-type.
5. The manufacturing process of claim 1 , wherein, in step 3, the ion implantation is carried out with a high ion dose and a low ion implant energy of less than 30 keV; wherein, if phosphorus, arsenic, antimony, titanium, or indium are implanted, the high ion dose is 1×10 14 ˜1×10 16 atoms per square centimeter, and if boron or boron fluoride is implanted, the high ion dose is 10 13 ˜1×10 16 atoms per square centimeter.
6. The manufacturing process of claim 1 , wherein, in step 7, the one or more ion implantations are conducted with a medium to low dose with an ion dose concentration of less than 1×10 14 atoms per square centimeter.