Split charge storage node outer spacer process
View Patent ↗Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
1. A memory cell, comprising:
two split sub-lithographic charge storage nodes on a semiconductor substrate;
two split sub-lithographic first poly gates on the two split sub-lithographic charge storage nodes, wherein the two split sub-lithographic first poly gates are formed by a removal of a portion of a patterned first poly surface between sloping surfaces of two spacers;
implanted portions in the semiconductor substrate under the two split sub-lithographic charge storage nodes;
a dielectric between the two split sub-lithographic charge storage nodes on the semiconductor substrate, the dielectric comprising a single layer, wherein the two spacers are formed on adjacent side surfaces of the dielectric and on portions of upper surfaces of the patterned first poly surface;
a second poly gate between the two split sub-lithographic charge storage nodes; and
a third poly gate over the semiconductor substrate.
2. The memory cell of claim 1 , wherein the two sub-lithographic charge storage nodes comprise nitrides.
3. The memory cell of claim 1 , wherein the dielectric between the two split sub-lithographic charge storage nodes comprises oxides.
4. The memory cell of claim 1 , wherein the two sub-lithographic charge storage nodes have a length of about 5 nm or more and about 50 nm or less.
5. The memory cell of claim 1 , further comprising a channel with a length of about 40 nm or more and about 200 nm or less.
6. A semiconductor structure comprising plural memory cells of claim 1 , wherein a bit line pitch of the plural memory cells is about 60 nm or more and about 350 nm or less.
7. A semiconductor structure comprising plural memory cells of claim 1 , wherein a bit line pitch of the plural memory cells is about 80 nm or more and about 310 nm or less.
8. The memory cell of claim 1 , wherein the two split sub-lithographic charge storage nodes have a length of about 10 nm or more and about 40 nm or less.
9. The memory cell of claim 1 , wherein the two split sub-lithographic charge storage nodes have a length of about 15 nm or more and about 35 nm or less.
10. The memory cell of claim 1 , wherein the two split sub-lithographic first poly gates have a length of about 5 nm or more and about 50 nm or less.
11. A memory cell, comprising:
two split sub-lithographic charge storage nodes on a semiconductor substrate, the two sub-lithographic charge storage nodes have a length of about 5 nm or more and about 50 nm or less;
two split sub-lithographic first poly gates on the two split sub-lithographic charge storage nodes the two split sub-lithographic first poly gates have a length of about 5 nm or more and about 50 nm or less, wherein the two split sub-lithographic first poly gates are formed by a removal of a portion of a patterned first poly surface between sloping surfaces of two spacers;
implanted portions in the semiconductor substrate under the two split sub-lithographic charge storage nodes;
a dielectric between the two split sub-lithographic charge storage nodes on the semiconductor substrate, the dielectric comprising a single layer, wherein the two spacers are formed on adjacent side surfaces of the dielectric and on portions of upper surfaces of the patterned first poly surface;
a second poly gate between the two split sub-lithographic charge storage nodes; and
a third poly gate over the semiconductor substrate.
12. The memory cell of claim 11 , wherein the two split sub-lithographic charge storage nodes comprise silicon rich silicon nitride.
13. The memory cell of claim 11 , further comprising a channel that has a length of about 40 nm or more and about 200 nm or less.
14. A semiconductor structure comprising plural memory cells of claim 11 , wherein a bit line pitch of the plural memory cells is about 60 nm or more and about 350 nm or less.
15. A semiconductor structure comprising plural memory cells of claim 11 , wherein a bit line pitch of the plural memory cells is about 80 nm or more and about 310 nm or less.
16. The memory cell of claim 11 , wherein the two split sub-lithographic charge storage nodes have a length of about 10 nm or more and about 40 nm or less.
17. The memory cell of claim 11 , wherein the two split sub-lithographic charge storage nodes have a length of about 15 nm or more and about 35 nm or less.
18. The memory cell of claim 11 , wherein the two split sub-lithographic first poly gates have a length of about 10 nm or more and about 40 nm or less.
19. A memory cell for storing two physically distinct bits, comprising:
two split sub-lithographic charge storage nodes on a semiconductor substrate, the two split sub-lithographic charge storage nodes each comprising three layers comprising a first and a second oxide layer sandwiching a charge storage silicon nitride layer;
two split sub-lithographic first poly gates on the two split sub-lithographic charge storage nodes, wherein the two split sub-lithographic first poly gates are formed by a removal of a portion of a patterned first poly surface between sloping surfaces of two spacers;
implanted portions in the semiconductor substrate under the two split sub-lithographic charge storage nodes;
a dielectric between the two split sub-lithographic charge storage nodes on the semiconductor substrate, the dielectric comprising a single layer, wherein the two spacers are formed on adjacent side surfaces of the dielectric and on portions of upper surfaces of the patterned first poly surface;
a second poly gate between the two split sub-lithographic charge storage nodes; and
a third poly gate over the semiconductor substrate.
20. The memory cell of claim 19 , wherein the charge storage silicon nitride layer of the two split sub-lithographic charge storage nodes comprises a silicon rich silicon nitride layer.